///////////////////////////////////////////////////////////////////////////////
//   ____  ____ 
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version : 2.1
//  \   \         Application : 7 Series FPGAs Transceivers Wizard
//  /   /         Filename : gige_sfp_gtwizard.v
// /___/   /\     
// \   \  /  \ 
//  \___\/\___\
//
//
// Module GTWIZARD (a GT Wrapper)
// Generated by Xilinx 7 Series FPGAs Transceivers Wizard
// 
// 
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
// 
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
// 
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`default_nettype wire

`timescale 1ns / 1ps
`define DLY #1

//***************************** Entity Declaration ****************************

(* CORE_GENERATION_INFO = "gige_sfp_GTWIZARD,gtwizard_v2_2,{protocol_file=gigabit_ethernet_CC}" *) module gige_sfp_GTWIZARD #






(
    // Simulation attributes
    parameter   WRAPPER_SIM_GTRESET_SPEEDUP    =   "false",     // Set to "true" to speed up sim reset
    parameter   RX_DFE_KL_CFG2_IN              =   32'h3010D90C,
    parameter   PMA_RSV_IN                     =   32'h00018480,
    parameter   SIM_VERSION                    =   "3.0"
)
(
    //_________________________________________________________________________
    //_________________________________________________________________________
    //GT0  (X0Y4)
    //____________________________CHANNEL PORTS________________________________
    //----------------------- Channel - Ref Clock Ports ------------------------
    input           GT0_GTREFCLK0_IN,
    //------------------------------ Channel PLL -------------------------------
    output          GT0_CPLLFBCLKLOST_OUT,
    output          GT0_CPLLLOCK_OUT,
    input           GT0_CPLLLOCKDETCLK_IN,
    output          GT0_CPLLREFCLKLOST_OUT,
    input           GT0_CPLLRESET_IN,
    //----------------------------- Eye Scan Ports -----------------------------
    output          GT0_EYESCANDATAERROR_OUT,
    //---------------------- Loopback and Powerdown Ports ----------------------
    input   [2:0]   GT0_LOOPBACK_IN,
    input   [1:0]   GT0_RXPD_IN,
    input   [1:0]   GT0_TXPD_IN,
    //----------------------------- Receive Ports ------------------------------
    input           GT0_RXUSERRDY_IN,
    //--------------------- Receive Ports - 8b10b Decoder ----------------------
    output  [1:0]   GT0_RXCHARISCOMMA_OUT,
    output  [1:0]   GT0_RXCHARISK_OUT,
    output  [1:0]   GT0_RXDISPERR_OUT,
    output  [1:0]   GT0_RXNOTINTABLE_OUT,
    //----------------- Receive Ports - Clock Correction Ports -----------------
    output  [1:0]   GT0_RXCLKCORCNT_OUT,
    //------------- Receive Ports - Comma Detection and Alignment --------------
    input           GT0_RXMCOMMAALIGNEN_IN,
    input           GT0_RXPCOMMAALIGNEN_IN,
    //----------------- Receive Ports - RX Data Path interface -----------------
    input           GT0_GTRXRESET_IN,
    output  [15:0]  GT0_RXDATA_OUT,
    output          GT0_RXOUTCLK_OUT,
    input           GT0_RXPCSRESET_IN,
    input           GT0_RXUSRCLK_IN,
    input           GT0_RXUSRCLK2_IN,
    //----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
    input           GT0_GTXRXN_IN,
    input           GT0_GTXRXP_IN,
    output          GT0_RXCDRLOCK_OUT,
    output          GT0_RXELECIDLE_OUT,
    //------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
    input           GT0_RXBUFRESET_IN,
    output  [2:0]   GT0_RXBUFSTATUS_OUT,
    //---------------------- Receive Ports - RX PLL Ports ----------------------
    output          GT0_RXRESETDONE_OUT,
    //----------------------------- Transmit Ports -----------------------------
    input           GT0_TXUSERRDY_IN,
    //-------------- Transmit Ports - 8b10b Encoder Control Ports --------------
    input   [1:0]   GT0_TXCHARDISPMODE_IN,
    input   [1:0]   GT0_TXCHARDISPVAL_IN,
    input   [1:0]   GT0_TXCHARISK_IN,
    //---------- Transmit Ports - TX Buffer and Phase Alignment Ports ----------
    output  [1:0]   GT0_TXBUFSTATUS_OUT,
    //---------------- Transmit Ports - TX Data Path interface -----------------
    input           GT0_GTTXRESET_IN,
    input   [15:0]  GT0_TXDATA_IN,
    output          GT0_TXOUTCLK_OUT,
    output          GT0_TXOUTCLKFABRIC_OUT,
    output          GT0_TXOUTCLKPCS_OUT,
    input           GT0_TXPCSRESET_IN,
    input           GT0_TXUSRCLK_IN,
    input           GT0_TXUSRCLK2_IN,
    //-------------- Transmit Ports - TX Driver and OOB signaling --------------
    output          GT0_GTXTXN_OUT,
    output          GT0_GTXTXP_OUT,
    //--------------------- Transmit Ports - TX PLL Ports ----------------------
    output          GT0_TXRESETDONE_OUT




);

//***************************** Wire Declarations *****************************

    // ground and vcc signals
    wire            tied_to_ground_i;
    wire    [63:0]  tied_to_ground_vec_i;
    wire            tied_to_vcc_i;
    wire    [63:0]  tied_to_vcc_vec_i;

    wire            gt0_qpllclk_i;
    wire            gt0_qpllrefclk_i;

         
//********************************* Main Body of Code**************************

    assign tied_to_ground_i             = 1'b0;
    assign tied_to_ground_vec_i         = 64'h0000000000000000;
    assign tied_to_vcc_i                = 1'b1;
    assign tied_to_vcc_vec_i            = 64'hffffffffffffffff;


      
//------------------------- GT Instances  -------------------------------
    //_________________________________________________________________________
    //_________________________________________________________________________
    //GT0  (X0Y4)

    gige_sfp_GTWIZARD_GT #
    (
        // Simulation attributes
        .GT_SIM_GTRESET_SPEEDUP   (WRAPPER_SIM_GTRESET_SPEEDUP),
        .SIM_VERSION              (SIM_VERSION),
        .RX_DFE_KL_CFG2_IN        (RX_DFE_KL_CFG2_IN),
        .PCS_RSVD_ATTR_IN         (48'h000000000000),
        .PMA_RSV_IN               (PMA_RSV_IN)
    )
    gt0_GTWIZARD_i
    (
        //----------------------- Channel - Ref Clock Ports ------------------------
        .GTREFCLK0_IN                   (GT0_GTREFCLK0_IN),
        //------------------------------ Channel PLL -------------------------------
        .CPLLFBCLKLOST_OUT              (GT0_CPLLFBCLKLOST_OUT),
        .CPLLLOCK_OUT                   (GT0_CPLLLOCK_OUT),
        .CPLLLOCKDETCLK_IN              (GT0_CPLLLOCKDETCLK_IN),
        .CPLLREFCLKLOST_OUT             (GT0_CPLLREFCLKLOST_OUT),
        .CPLLRESET_IN                   (GT0_CPLLRESET_IN),
        //----------------------------- Eye Scan Ports -----------------------------
        .EYESCANDATAERROR_OUT           (GT0_EYESCANDATAERROR_OUT),
        //---------------------- Loopback and Powerdown Ports ----------------------
        .LOOPBACK_IN                    (GT0_LOOPBACK_IN),
        .RXPD_IN                        (GT0_RXPD_IN),
        .TXPD_IN                        (GT0_TXPD_IN),
        //----------------------------- Receive Ports ------------------------------
        .RXUSERRDY_IN                   (GT0_RXUSERRDY_IN),
        //--------------------- Receive Ports - 8b10b Decoder ----------------------
        .RXCHARISCOMMA_OUT              (GT0_RXCHARISCOMMA_OUT),
        .RXCHARISK_OUT                  (GT0_RXCHARISK_OUT),
        .RXDISPERR_OUT                  (GT0_RXDISPERR_OUT),
        .RXNOTINTABLE_OUT               (GT0_RXNOTINTABLE_OUT),
        //----------------- Receive Ports - Clock Correction Ports -----------------
        .RXCLKCORCNT_OUT                (GT0_RXCLKCORCNT_OUT),
        //------------- Receive Ports - Comma Detection and Alignment --------------
        .RXMCOMMAALIGNEN_IN             (GT0_RXMCOMMAALIGNEN_IN),
        .RXPCOMMAALIGNEN_IN             (GT0_RXPCOMMAALIGNEN_IN),
        //----------------- Receive Ports - RX Data Path interface -----------------
        .GTRXRESET_IN                   (GT0_GTRXRESET_IN),
        .RXDATA_OUT                     (GT0_RXDATA_OUT),
        .RXOUTCLK_OUT                   (GT0_RXOUTCLK_OUT),
        .RXPCSRESET_IN                  (GT0_RXPCSRESET_IN),
        .RXUSRCLK_IN                    (GT0_RXUSRCLK_IN),
        .RXUSRCLK2_IN                   (GT0_RXUSRCLK2_IN),
        //----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
        .GTXRXN_IN                      (GT0_GTXRXN_IN),
        .GTXRXP_IN                      (GT0_GTXRXP_IN),
        .RXCDRLOCK_OUT                  (GT0_RXCDRLOCK_OUT),
        .RXELECIDLE_OUT                 (GT0_RXELECIDLE_OUT),
        //------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
        .RXBUFRESET_IN                  (GT0_RXBUFRESET_IN),
        .RXBUFSTATUS_OUT                (GT0_RXBUFSTATUS_OUT),
        //---------------------- Receive Ports - RX PLL Ports ----------------------
        .RXRESETDONE_OUT                (GT0_RXRESETDONE_OUT),
        //----------------------------- Transmit Ports -----------------------------
        .TXUSERRDY_IN                   (GT0_TXUSERRDY_IN),
        //-------------- Transmit Ports - 8b10b Encoder Control Ports --------------
        .TXCHARDISPMODE_IN              (GT0_TXCHARDISPMODE_IN),
        .TXCHARDISPVAL_IN               (GT0_TXCHARDISPVAL_IN),
        .TXCHARISK_IN                   (GT0_TXCHARISK_IN),
        //---------- Transmit Ports - TX Buffer and Phase Alignment Ports ----------
        .TXBUFSTATUS_OUT                (GT0_TXBUFSTATUS_OUT),
        //---------------- Transmit Ports - TX Data Path interface -----------------
        .GTTXRESET_IN                   (GT0_GTTXRESET_IN),
        .TXDATA_IN                      (GT0_TXDATA_IN),
        .TXOUTCLK_OUT                   (GT0_TXOUTCLK_OUT),
        .TXOUTCLKFABRIC_OUT             (GT0_TXOUTCLKFABRIC_OUT),
        .TXOUTCLKPCS_OUT                (GT0_TXOUTCLKPCS_OUT),
        .TXPCSRESET_IN                  (GT0_TXPCSRESET_IN),
        .TXUSRCLK_IN                    (GT0_TXUSRCLK_IN),
        .TXUSRCLK2_IN                   (GT0_TXUSRCLK2_IN),
        //-------------- Transmit Ports - TX Driver and OOB signaling --------------
        .GTXTXN_OUT                     (GT0_GTXTXN_OUT),
        .GTXTXP_OUT                     (GT0_GTXTXP_OUT),
        //--------------------- Transmit Ports - TX PLL Ports ----------------------
        .TXRESETDONE_OUT                (GT0_TXRESETDONE_OUT)

    );
endmodule


