                                                          Log file                                                       

Generated by MIG MIG Version 1.8
Coregen 14.4 - Build Number P.49d on Tue Jan 15 12:47:00 2013


Creating the directory 
/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface/example_design
Created the UCF file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface/example_design/par/example_top.ucf Successfully
Created the SDC file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface/example_design/par/example_top.xdc Successfully
Copied the Traffic Gen Files Successfully
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface/example_design/rtl/ddr2_ddr3_chipscope.v Successfully
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Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface/example_design/rtl/mig_7series_v1_8_chk_win.v Successfully
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Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface/example_design/../docs/phy_only_support_readme.txt Successfully
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Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface/example_design/par/create_ise.sh Successfully
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Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface/example_design/par/makeproj.sh Successfully
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Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface/example_design/par/rem_files.sh Successfully
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Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface/example_design/par/ise_flow.sh Successfully
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Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface/example_design/par/vivado.tcl Successfully
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Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface/example_design/par/vivado_gui.tcl Successfully
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Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface/example_design/par/rem_files.tcl Successfully
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Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface/example_design/par/set_ise_prop.tcl Successfully
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Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface/example_design/par/readme.txt Successfully
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Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface/example_design/par/xst_options.txt Successfully
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Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface/example_design/par/ddr_icon_cg.xco Successfully
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Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface/example_design/par/ddr_ila_basic_cg.xco Successfully
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Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface/example_design/par/ddr_ila_wrpath_cg.xco Successfully
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Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface/example_design/par/ddr_ila_rdpath_cg.xco Successfully
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Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface/example_design/par/ddr_vio_sync_async_out72_cg.xco Successfully
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Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface/example_design/par/ddr_vio_async_in_sync_out_cg.xco Successfully
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Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface/example_design/par/example_top.cdc Successfully
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Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface/example_design/par/example_top.cpj Successfully
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Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface/example_design/sim/ddr3_model.v Successfully
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Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface/example_design/sim/ddr3_model_parameters.vh Successfully
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Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface/example_design/sim/isim_files.prj Successfully
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Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface/example_design/sim/isim_options.tcl Successfully
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Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface/example_design/sim/isim_run.sh Successfully
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Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface/example_design/sim/xsim_files.prj Successfully
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Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface/example_design/sim/xsim_options.tcl Successfully
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Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface/example_design/sim/xsim_run.sh Successfully
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Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface/example_design/sim/readme.txt Successfully
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Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface/example_design/sim/sim.do Successfully
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Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface/example_design/sim/sim_tb_top.v Successfully
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Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface/example_design/sim/wiredly.v Successfully
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Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface/example_design/synth/example_top.lso Successfully
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Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface/example_design/synth/example_top.prj Successfully
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Created the Top Level File - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface/example_design/rtl/example_top.v
Created the Top Level File - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface/example_design/sim/sim_tb_top.v
The design output files are located in /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface/example_design/rtl and ..example_design/par for rtl & ucf files respectively.
