////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: P.49d
//  \   \         Application: netgen
//  /   /         Filename: ten_gig_eth_pcs_pma.v
// /___/   /\     Timestamp: Mon Jan 28 16:53:26 2013
// \   \  /  \ 
//  \___\/\___\
//             
// Command	: -w -sim -ofmt verilog /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/x300/coregen/tmp/_cg/ten_gig_eth_pcs_pma.ngc /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/x300/coregen/tmp/_cg/ten_gig_eth_pcs_pma.v 
// Device	: 7k410tffg900-2
// Input file	: /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/x300/coregen/tmp/_cg/ten_gig_eth_pcs_pma.ngc
// Output file	: /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/x300/coregen/tmp/_cg/ten_gig_eth_pcs_pma.v
// # of Modules	: 1
// Design Name	: ten_gig_eth_pcs_pma
// Xilinx        : /opt/Xilinx/14.4/ISE_DS/ISE/
//             
// Purpose:    
//     This verilog netlist is a verification model and uses simulation 
//     primitives which may not represent the true implementation of the 
//     device, however the netlist is functionally correct and should not 
//     be modified. This file cannot be synthesized and should only be used 
//     with supported simulation tools.
//             
// Reference:  
//     Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//             
////////////////////////////////////////////////////////////////////////////////

`timescale 1 ns/1 ps

module ten_gig_eth_pcs_pma (
  reset, txreset322, rxreset322, dclk_reset, clk156, txusrclk2, rxusrclk2, dclk, mdc, mdio_in, resetdone, drp_gnt, drp_drdy, signal_detect, tx_fault, 
pma_resetout, pcs_resetout, mdio_out, mdio_tri, gt_slip, drp_req, drp_den, drp_dwe, tx_disable, tx_prbs31_en, rx_prbs31_en, clear_rx_prbs_err_count, 
xgmii_txd, xgmii_txc, prtad, pma_pmd_type, gt_rxd, gt_rxc, drp_drpdo, xgmii_rxd, xgmii_rxc, core_status, gt_txd, gt_txc, drp_daddr, drp_di, 
loopback_ctrl
)/* synthesis syn_black_box syn_noprune=1 */;
  input reset;
  input txreset322;
  input rxreset322;
  input dclk_reset;
  input clk156;
  input txusrclk2;
  input rxusrclk2;
  input dclk;
  input mdc;
  input mdio_in;
  input resetdone;
  input drp_gnt;
  input drp_drdy;
  input signal_detect;
  input tx_fault;
  output pma_resetout;
  output pcs_resetout;
  output mdio_out;
  output mdio_tri;
  output gt_slip;
  output drp_req;
  output drp_den;
  output drp_dwe;
  output tx_disable;
  output tx_prbs31_en;
  output rx_prbs31_en;
  output clear_rx_prbs_err_count;
  input [63 : 0] xgmii_txd;
  input [7 : 0] xgmii_txc;
  input [4 : 0] prtad;
  input [2 : 0] pma_pmd_type;
  input [31 : 0] gt_rxd;
  input [7 : 0] gt_rxc;
  input [15 : 0] drp_drpdo;
  output [63 : 0] xgmii_rxd;
  output [7 : 0] xgmii_rxc;
  output [7 : 0] core_status;
  output [31 : 0] gt_txd;
  output [7 : 0] gt_txc;
  output [15 : 0] drp_daddr;
  output [15 : 0] drp_di;
  output [2 : 0] loopback_ctrl;
  
  // synthesis translate_off
  
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_5/d ;
  wire \NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/q ;
  wire \NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_0/q_0 ;
  wire \NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15/q_0 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_out_259 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_tri_260 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_slip_261 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_4/d2_262 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[0].synch_inst/q_263 ;
  wire \NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/q ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clear_rx_prbs_err_count_265 ;
  wire N0;
  wire NlwRenamedSig_OI_drp_dwe;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resets_resyncs_i/resynch[0].synch_inst/d1_d_MUX_806_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resets_resyncs_i/resynch[0].synch_inst/q_d1_MUX_807_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/q_d1_MUX_807_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/d1_d_MUX_806_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/d1_272 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/q_d1_MUX_807_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/d1_d_MUX_806_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/d1_275 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/q_d1_MUX_807_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/d1_d_MUX_806_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/d1_278 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/q_d1_MUX_807_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/d1_281 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[0].synch_inst/q_d1_MUX_807_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[0].synch_inst/d1_d_MUX_806_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[0].synch_inst/d1_284 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_d1_MUX_807_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[0].synch_inst/d1_d_MUX_806_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[0].synch_inst/q_d1_MUX_807_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/q_d1_MUX_807_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[1].synch_inst/q_d1_MUX_807_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[2].synch_inst/q_d1_MUX_807_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_5/d1_292 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_4/d1_293 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rxreset_local_430 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_test_mode_int_pcs_rxreset_AND_376_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_reset_clear_core_int ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_slip_int_reg_499 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[2].synch_inst/d1_d_MUX_806_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_test_mode_int_reg_501 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_slip_reg_502 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxheadervalid_503 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxdatavalid_504 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resets_resyncs_i/resynch[0].synch_inst/q_539 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[0].synch_inst/q_540 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/q_541 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/q_542 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/q_543 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clear_test_pattern_err_count_reg_545 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/prbs31_rx_enable_core_reg_546 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_reset_clear_core_intr_547 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[1].synch_inst/q_548 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[2].synch_inst/q_549 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_5/d2_550 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_count_inc_551 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_806_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/err_block_count_inc_out_554 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_555 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_out_694 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_out_695 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_out_696 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_rxreset ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_0_699 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_1_700 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_2_701 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_3_702 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_4_703 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_5_704 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_6_705 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_7_706 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_8_707 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_9_708 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_10_709 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_11_710 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_12_711 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_13_712 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_14_713 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_15_714 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_16_715 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_17_716 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_18_717 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_19_718 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_20_719 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_21_720 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_22_721 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_23_722 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_24_723 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_25_724 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_26_725 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_27_726 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_28_727 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_29_728 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_30_729 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_31_730 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_32_731 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_33_732 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_34_733 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_35_734 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_36_735 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_37_736 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_38_737 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_39_738 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_40_739 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_41_740 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_42_741 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_43_742 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_44_743 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_45_744 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_46_745 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_47_746 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_48_747 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_49_748 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_50_749 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_51_750 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_52_751 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_53_752 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_54_753 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_55_754 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_56_755 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_57_756 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_58_757 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_59_758 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_60_759 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_61_760 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_62_761 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_63_762 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_64_763 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_65_764 ;
  wire NlwRenamedSig_OI_pcs_resetout;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/full_int_838 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clear_test_pattern_err_count ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/prbs31_tx_enable_core_int ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/prbs31_rx_enable_core_int ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_4/d ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rdack ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT<4> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT<5> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT<6> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT<7> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT<8> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT<9> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT<10> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT<11> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT<12> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT<13> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT<14> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT<15> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/wrack_1244 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rdack_1245 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_11/q_0_1250 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_11/q_0_1251 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_rnw ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_cs ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_reg1_GND_62_o_MUX_766_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_in_GND_62_o_MUX_765_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_in_reg3_1336 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_in_reg2_1337 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_in_reg1_1338 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_we_rising_1339 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_we_reg_1340 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1341 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_reg3_1342 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_reg1_1343 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_reg2_1344 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1361 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/we_1362 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg[4]_GND_63_o_equal_123_o<4>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>3 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>3 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>3 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1-In1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>2 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>2 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>2 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1_1437 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>1_1438 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1_1439 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<14>_1441 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<13>_1442 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<12>_1443 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<11>_1444 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<10>_1445 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<9>_1446 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<8>_1447 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<7>_1448 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<6>_1449 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<5>_1450 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<4>_1451 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<3>_1452 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<2>_1453 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<1>_1454 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<0>_1455 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_lut<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<14>_1457 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<13>_1458 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<12>_1459 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<11>_1460 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<10>_1461 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<9>_1462 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<8>_1463 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<7>_1464 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<6>_1465 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<5>_1466 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<4>_1467 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<3>_1468 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<2>_1469 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<1>_1470 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<0>_1471 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_lut<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<14>_1473 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<13>_1474 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<12>_1475 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<11>_1476 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<10>_1477 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<9>_1478 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<8>_1479 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<7>_1480 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<6>_1481 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<5>_1482 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<4>_1483 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<3>_1484 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<2>_1485 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<1>_1486 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<0>_1487 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_lut<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mcount_bit_count_eqn_4_1489 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mcount_bit_count_eqn_3 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mcount_bit_count_eqn_2 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mcount_bit_count_eqn_1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mcount_bit_count_eqn_0 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0262_inv ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1_1495 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2_1496 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3_1497 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1498 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1-In_1499 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2-In ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3-In ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4-In_1502 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0267_inv ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0271_inv ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad[4]_devad[4]_OR_530_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_PWR_65_o_not_equal_135_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_PWR_65_o_not_equal_129_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_PWR_65_o_not_equal_132_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/n0027 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<4> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<5> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<6> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<7> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<8> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<9> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<10> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<11> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<12> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<13> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<14> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<15> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<4> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<5> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<6> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<7> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<8> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<9> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<10> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<11> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<12> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<13> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<14> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<15> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<4> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<5> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<6> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<7> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<8> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<9> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<10> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<11> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<12> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<13> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<14> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<15> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_tri_int ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_out_int ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count_load_en ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<4> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<5> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<6> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<7> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<8> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<9> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<10> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<11> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<12> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<13> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<14> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<15> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<4> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<5> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<6> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<7> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<8> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<9> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<10> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<11> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<12> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<13> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<14> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<15> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<4> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<5> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<6> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<7> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<8> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<9> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<10> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<11> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<12> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<13> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<14> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<15> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_351_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_just_rose_opcode[1]_AND_362_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<4> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<5> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<6> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<7> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<8> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<9> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<10> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<11> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<12> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<13> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<14> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<15> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0256 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_350_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_347_o_1631 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_in_reg_1632 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_match_1644 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_just_rose_1645 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_reg_1646 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[8]_prtad[4]_equal_89_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_0 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3-In ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2-In1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1-In1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_read_AND_368_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/_n0084 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_366_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1673 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/indirect_read_1676 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT14211 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT171 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_reg_1_0[15]_select_26_OUT<0>2 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_PWR_46_o_equal_57_o<15>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[20]_GND_44_o_equal_101_o<20>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_addrdecode2 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_35_o<15>1_1724 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_48_o<15>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1726 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039717 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode2 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_addrdecode1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039771 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q[9]_d[9]_mux_3_OUT<9> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q[9]_d[9]_mux_3_OUT<8> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q[9]_d[9]_mux_3_OUT<7> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q[9]_d[9]_mux_3_OUT<6> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q[9]_d[9]_mux_3_OUT<5> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q[9]_d[9]_mux_3_OUT<4> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q[9]_d[9]_mux_3_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q[9]_d[9]_mux_3_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q[9]_d[9]_mux_3_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q[9]_d[9]_mux_3_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q[9]_d[9]_mux_3_OUT<9> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q[9]_d[9]_mux_3_OUT<8> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q[9]_d[9]_mux_3_OUT<7> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q[9]_d[9]_mux_3_OUT<6> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q[9]_d[9]_mux_3_OUT<5> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q[9]_d[9]_mux_3_OUT<4> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q[9]_d[9]_mux_3_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q[9]_d[9]_mux_3_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q[9]_d[9]_mux_3_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q[9]_d[9]_mux_3_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_8_10/re_prev_1753 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_8_10/re_prev_1754 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_14/_n0014 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_1_2/re_prev_1756 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_1_2/re_prev_1757 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_0/q[0]_d[0]_MUX_691_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_11/q[0]_d[0]_MUX_691_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_11/q[0]_d[0]_MUX_691_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_14/q[0]_d[0]_MUX_691_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<15> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<14> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<13> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<12> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<11> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<10> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<9> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<8> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<7> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<6> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<5> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<4> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<15> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<14> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<13> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<12> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<11> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<10> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<9> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<8> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<7> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<6> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<5> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<4> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<15> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<14> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<13> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<12> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<11> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<10> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<9> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<8> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<7> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<6> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<5> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<4> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q[15]_d[15]_mux_3_OUT<15> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q[15]_d[15]_mux_3_OUT<14> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q[15]_d[15]_mux_3_OUT<13> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q[15]_d[15]_mux_3_OUT<12> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q[15]_d[15]_mux_3_OUT<11> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q[15]_d[15]_mux_3_OUT<10> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q[15]_d[15]_mux_3_OUT<9> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q[15]_d[15]_mux_3_OUT<8> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q[15]_d[15]_mux_3_OUT<7> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q[15]_d[15]_mux_3_OUT<6> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q[15]_d[15]_mux_3_OUT<5> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q[15]_d[15]_mux_3_OUT<4> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q[15]_d[15]_mux_3_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q[15]_d[15]_mux_3_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q[15]_d[15]_mux_3_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q[15]_d[15]_mux_3_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q[15]_d[15]_mux_3_OUT<15> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q[15]_d[15]_mux_3_OUT<14> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q[15]_d[15]_mux_3_OUT<13> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q[15]_d[15]_mux_3_OUT<12> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q[15]_d[15]_mux_3_OUT<11> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q[15]_d[15]_mux_3_OUT<10> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q[15]_d[15]_mux_3_OUT<9> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q[15]_d[15]_mux_3_OUT<8> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q[15]_d[15]_mux_3_OUT<7> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q[15]_d[15]_mux_3_OUT<6> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q[15]_d[15]_mux_3_OUT<5> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q[15]_d[15]_mux_3_OUT<4> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q[15]_d[15]_mux_3_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q[15]_d[15]_mux_3_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q[15]_d[15]_mux_3_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q[15]_d[15]_mux_3_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<15> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<14> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<13> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<12> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<11> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<10> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<9> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<8> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<7> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<6> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<5> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<4> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q[15]_d[15]_mux_3_OUT<15> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q[15]_d[15]_mux_3_OUT<14> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q[15]_d[15]_mux_3_OUT<13> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q[15]_d[15]_mux_3_OUT<12> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q[15]_d[15]_mux_3_OUT<11> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q[15]_d[15]_mux_3_OUT<10> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q[15]_d[15]_mux_3_OUT<9> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q[15]_d[15]_mux_3_OUT<8> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q[15]_d[15]_mux_3_OUT<7> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q[15]_d[15]_mux_3_OUT<6> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q[15]_d[15]_mux_3_OUT<5> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q[15]_d[15]_mux_3_OUT<4> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q[15]_d[15]_mux_3_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q[15]_d[15]_mux_3_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q[15]_d[15]_mux_3_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q[15]_d[15]_mux_3_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<15> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<14> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<13> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<12> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<11> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<10> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<9> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<8> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<7> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<6> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<5> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<4> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rnw_inv ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_we ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_we ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_35_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rdack_rdack_OR_520_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_we ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_we ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_we ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_we ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_we ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_we ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_we ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_we ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_we ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_9_we ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15_we ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15_we ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_8_10/q_0_1926 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_8_11/q_0_1927 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_36_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_42_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_40_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_43_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_54_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_53_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_52_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_51_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_47_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_46_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_45_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_PWR_46_o_equal_60_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_PWR_46_o_equal_56_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/_n0398 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/wrack_cs_AND_303_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_re ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_re ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_8_re ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_1_re ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_8_re ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_1_re ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_14/q_0_1952 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_15/q_0_1953 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_32_0/q_0_1954 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_32_1/q_0_1955 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_32_12/q_0_1956 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_1_2/q_0_1957 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_10_0/q_0_1959 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_1_2/q_0_1960 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/re_rising ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_15/re_prev_1998 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/q[5]_GND_50_o_mux_3_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/q[5]_GND_50_o_mux_3_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/q[5]_GND_50_o_mux_3_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/q[5]_GND_50_o_mux_3_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/q[5]_GND_50_o_mux_3_OUT<4> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/q[5]_GND_50_o_mux_3_OUT<5> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q[7]_GND_51_o_mux_3_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q[7]_GND_51_o_mux_3_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q[7]_GND_51_o_mux_3_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q[7]_GND_51_o_mux_3_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q[7]_GND_51_o_mux_3_OUT<4> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q[7]_GND_51_o_mux_3_OUT<5> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q[7]_GND_51_o_mux_3_OUT<6> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q[7]_GND_51_o_mux_3_OUT<7> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/re_rising ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/re_prev_2014 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q[15]_GND_55_o_mux_3_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q[15]_GND_55_o_mux_3_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q[15]_GND_55_o_mux_3_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q[15]_GND_55_o_mux_3_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q[15]_GND_55_o_mux_3_OUT<4> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q[15]_GND_55_o_mux_3_OUT<5> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q[15]_GND_55_o_mux_3_OUT<6> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q[15]_GND_55_o_mux_3_OUT<7> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q[15]_GND_55_o_mux_3_OUT<8> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q[15]_GND_55_o_mux_3_OUT<9> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q[15]_GND_55_o_mux_3_OUT<10> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q[15]_GND_55_o_mux_3_OUT<11> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q[15]_GND_55_o_mux_3_OUT<12> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q[15]_GND_55_o_mux_3_OUT<13> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q[15]_GND_55_o_mux_3_OUT<14> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q[15]_GND_55_o_mux_3_OUT<15> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/_n0012_inv ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<4> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<5> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<6> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<7> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<8> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<9> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<10> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<11> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<12> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<13> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<14> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<15> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_wrack_dclk ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rdack_dclk ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1-In ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2-In ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0071_inv ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0063_inv ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0059_inv ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0067_inv ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_INV_322_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<32> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<33> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2079 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2080 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2081 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0037 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0043 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0045 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0040 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<4> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<5> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<6> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<7> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<8> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<9> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<10> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<11> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<12> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<13> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<14> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<15> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<16> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<17> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<7>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<6>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<5>2 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<4>2 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<3>2 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<2>2 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<1>2 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<0>2 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<5>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<4>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<3>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<2>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<1>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<0>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count_control_core_i_pcs_error_block_count[7]_AND_186_o_2239 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count_control_core_i_pcs_ber_count[5]_AND_185_o_2240 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_395_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_error_block_count_OR_394_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/_n00791_2243 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Mcount_txsequence_int_val ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/_n0079 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/read_enable_2252 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Result<3>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Result<2>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Result<1>1_2327 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Result<0>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/emptyg ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/fullg ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2]_rd_addr[1]_XOR_3_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3]_rd_addr[2]_XOR_2_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2]_wr_addr[1]_XOR_6_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3]_wr_addr[2]_XOR_5_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/empty_int_2366 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rag_writesync0[3]_GND_15_o_mux_66_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rag_writesync0[3]_GND_15_o_mux_66_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rag_writesync0[3]_GND_15_o_mux_66_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rag_writesync0[3]_GND_15_o_mux_66_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_truegray[3]_GND_15_o_mux_65_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_truegray[3]_GND_15_o_mux_65_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_truegray[3]_GND_15_o_mux_65_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_truegray[3]_GND_15_o_mux_65_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/can_insert ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/can_insert_wra_comb ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/can_insert_rd ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/can_insert_rd_tmp ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_en ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/can_insert_wra2 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/can_insert_wra ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1-In ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd2-In ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3-In ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out[7]_GND_34_o_mux_32_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out[7]_GND_34_o_mux_32_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out[7]_GND_34_o_mux_32_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out[7]_GND_34_o_mux_32_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out[7]_GND_34_o_mux_32_OUT<4> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out[7]_GND_34_o_mux_32_OUT<5> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out[7]_GND_34_o_mux_32_OUT<6> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out[7]_GND_34_o_mux_32_OUT<7> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<4> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<5> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<6> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<7> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<8> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<9> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<10> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<11> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<12> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<13> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<14> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<15> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<16> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<17> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<18> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<19> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<20> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<21> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<22> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<23> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<24> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<25> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<26> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<27> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<28> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<29> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<30> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<31> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<32> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<33> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<34> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<35> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<36> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<37> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<38> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<39> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<40> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<41> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<42> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<43> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<44> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<45> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<46> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<47> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<48> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<49> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<50> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<51> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<52> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<53> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<54> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<55> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<56> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<57> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<58> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<59> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<60> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<61> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<62> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<63> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_delay[7]_GND_34_o_mux_19_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_delay[7]_GND_34_o_mux_19_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_delay[7]_GND_34_o_mux_19_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_delay[7]_GND_34_o_mux_19_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<4> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<5> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<6> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<7> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<8> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<9> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<10> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<11> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<12> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<13> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<14> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<15> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<16> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<17> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<18> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<19> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<20> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<21> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<22> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<23> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<24> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<25> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<26> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<27> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<28> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<29> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<30> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<31> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_was_seq_2765 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_was_idle_2766 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3_2877 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd2_2878 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe[7]_GND_34_o_mux_7_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe[7]_GND_34_o_mux_7_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe[7]_GND_34_o_mux_7_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe[7]_GND_34_o_mux_7_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe[7]_GND_34_o_mux_7_OUT<4> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe[7]_GND_34_o_mux_7_OUT<5> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe[7]_GND_34_o_mux_7_OUT<6> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe[7]_GND_34_o_mux_7_OUT<7> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<4> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<5> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<6> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<7> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<8> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<9> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<10> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<11> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<12> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<13> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<14> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<15> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<16> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<17> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<18> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<19> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<20> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<21> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<22> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<23> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<24> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<25> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<26> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<27> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<28> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<29> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<30> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<31> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<32> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<33> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<34> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<35> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<36> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<37> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<38> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<39> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<40> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<41> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<42> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<43> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<44> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<45> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<46> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<47> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<48> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<49> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<50> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<51> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<52> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<53> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<54> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<55> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<56> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<57> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<58> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<59> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<60> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<61> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<62> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<63> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Msub_wr_addr_pipe[3]_ra_writesync[3]_sub_81_OUT_cy<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Result<3>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Result<2>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Result<1>1_2989 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Result<0>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/full_int_inv ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/_n0201_inv ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/_n0210_inv ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/emptyg ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/fullg ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr[2]_rd_addr[1]_XOR_510_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr[3]_rd_addr[2]_XOR_509_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe[3]_ra_writesync[3]_sub_81_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe[3]_ra_writesync[3]_sub_81_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray[3]_PWR_39_o_mux_31_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray[3]_PWR_39_o_mux_31_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray[3]_PWR_39_o_mux_31_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray[3]_PWR_39_o_mux_31_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_gray[3]_PWR_39_o_mux_25_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_gray[3]_PWR_39_o_mux_25_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_gray[3]_PWR_39_o_mux_25_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_gray[3]_PWR_39_o_mux_25_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_nextgray[3]_PWR_39_o_mux_19_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_nextgray[3]_PWR_39_o_mux_19_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_nextgray[3]_PWR_39_o_mux_19_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync0[3]_GND_37_o_mux_66_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync0[3]_GND_37_o_mux_66_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync0[3]_GND_37_o_mux_66_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync0[3]_GND_37_o_mux_66_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_truegray[3]_GND_37_o_mux_65_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_truegray[3]_GND_37_o_mux_65_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_truegray[3]_GND_37_o_mux_65_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_truegray[3]_GND_37_o_mux_65_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray[3]_PWR_39_o_mux_50_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray[3]_PWR_39_o_mux_50_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray[3]_PWR_39_o_mux_50_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray[3]_PWR_39_o_mux_50_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_nextgray[3]_PWR_39_o_mux_44_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_nextgray[3]_PWR_39_o_mux_44_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_nextgray[3]_PWR_39_o_mux_44_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/full_int_3072 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd3-In ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_in[7]_GND_39_o_mux_22_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_in[7]_GND_39_o_mux_22_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_in[7]_GND_39_o_mux_22_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_in[7]_GND_39_o_mux_22_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_in[7]_GND_39_o_mux_22_OUT<4> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_in[7]_GND_39_o_mux_22_OUT<5> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_in[7]_GND_39_o_mux_22_OUT<6> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_in[7]_GND_39_o_mux_22_OUT<7> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<4> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<5> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<6> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<7> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<8> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<9> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<10> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<11> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<12> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<13> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<14> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<15> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<16> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<17> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<18> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<19> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<20> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<21> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<22> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<23> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<24> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<25> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<26> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<27> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<28> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<29> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<30> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<31> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<32> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<33> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<34> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<35> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<36> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<37> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<38> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<39> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<40> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<41> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<42> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<43> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<44> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<45> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<46> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<47> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<48> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<49> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<50> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<51> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<52> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<53> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<54> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<55> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<56> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<57> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<58> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<59> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<60> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<61> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<62> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<63> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_in[7]_GND_39_o_mux_3_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_in[7]_GND_39_o_mux_3_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_in[7]_GND_39_o_mux_3_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_in[7]_GND_39_o_mux_3_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<4> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<5> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<6> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<7> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<8> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<9> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<10> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<11> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<12> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<13> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<14> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<15> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<16> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<17> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<18> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<19> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<20> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<21> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<22> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<23> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<24> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<25> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<26> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<27> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<28> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<29> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<30> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<31> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd3_3332 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd2_3333 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd1_3334 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/local_fault_3335 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_inv ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o_norst ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/eq_rxusrclk2_en156_3376 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxusrclk2_en156_dup2_3377 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxusrclk2_en156_dup1_3378 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/d1_3379 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/newedge_3380 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/newedge_reg_3381 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/out_comb ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/d1_3383 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/newedge_3384 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/newedge_reg_3385 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/out_comb ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/d1_3387 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/newedge_3388 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/newedge_reg_3389 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/out_comb ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_sync_1_counter_sync_extra_OR_558_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_1_3392 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_3_3393 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_2_3394 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_sync_extra_3395 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/q_3396 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/q_3397 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/q_3398 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/d1_3399 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/newedge_3400 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/newedge_reg_3401 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/out_comb ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/d1_3403 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/newedge_3404 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/newedge_reg_3405 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/out_comb ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/d1_3407 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/newedge_3408 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/newedge_reg_3409 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/out_comb ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_sync_1_counter_sync_extra_OR_558_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_1_3412 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_3_3413 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_2_3414 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_sync_extra_3415 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/q_3416 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/q_3417 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/q_3418 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/d1_3419 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/newedge_3420 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/newedge_reg_3421 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/out_comb ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/d1_3423 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/newedge_3424 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/newedge_reg_3425 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/out_comb ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/d1_3427 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/newedge_3428 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/newedge_reg_3429 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/out_comb ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_sync_1_counter_sync_extra_OR_558_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_1_3432 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_3_3433 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_2_3434 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_sync_extra_3435 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/q_3436 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/q_3437 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/q_3438 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT171211 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT232 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11322 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT522 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT143_3443 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11121 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT117111 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT111112 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11321 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT2811 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11411 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_PWR_23_o_equal_185_o3 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out142 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1711 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT92 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out232 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<1>11 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<1>11 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<1>11 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<1>11 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<1>11 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<1>11 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_453_o<7>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_GND_22_o_equal_151_o1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o<7>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out1411 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_445_o<7>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_PWR_23_o_equal_185_o2 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<4>3 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<4>3 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<4>3 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<4>3 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<4>3 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<4>3 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1141 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT31 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[47]_tx_xgmii_data_reg1[47]_OR_94_o2 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[31]_tx_xgmii_data_reg1[31]_OR_80_o2 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1162 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out141 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o<7>1_3480 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out231 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o<7>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n09151_3483 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>31 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<31>2 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<25>3_3486 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>111_3487 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<31>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<17>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>2 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<33>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<41>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>3 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT211 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<49>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>11 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<28>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>2 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<25>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<60>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[31]_PWR_23_o_equal_118_o_mmx_out ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[15]_PWR_23_o_equal_102_o_mmx_out ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[55]_PWR_23_o_equal_142_o_mmx_out_3506 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[47]_PWR_23_o_equal_134_o_mmx_out ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_126_o_mmx_out1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_PWR_23_o_equal_185_o_mmx_out ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_PWR_23_o_equal_185_o_mmx_out1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_166_o_mmx_out2 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[47]_PWR_23_o_equal_134_o_mmx_out1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2<37>_mmx_out ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2<36>_mmx_out1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2<37>_mmx_out2 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2<37>_mmx_out3 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2<5>_mmx_out ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2<4>_mmx_out1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2<5>_mmx_out2 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2<5>_mmx_out3 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n1230_inv ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n1043_inv ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<7>_inv ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<6>_inv ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<5>_inv ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<4>_inv ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<3>_inv ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<2>_inv ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<0>_inv ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<1>_inv ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[7]_reduce_and_188_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[3]_reduce_and_158_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[5]_AND_66_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[4]_AND_64_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[3]_AND_61_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[2]_AND_57_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[1]_AND_52_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[0] ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[1] ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[2] ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[3] ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[4] ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[6] ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[7] ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_tx_xgmii_data_reg1[39]_OR_153_o_3588 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[7]_tx_xgmii_data_reg1[7]_OR_155_o_3589 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_455_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_448_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_445_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_GND_22_o_equal_181_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_GND_22_o_equal_165_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[63]_PWR_23_o_equal_148_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_166_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_126_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[23]_PWR_23_o_equal_110_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[15]_PWR_23_o_equal_102_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[7]_PWR_23_o_equal_182_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/n0141 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n0854 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n0915 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n0856 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/n0153 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_reduce_and_78_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg[2]_GND_22_o_mux_458_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg[2]_GND_22_o_mux_458_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg[2]_GND_22_o_mux_458_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<4> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<5> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<6> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<7> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<8> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<9> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<10> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<11> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<12> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<13> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<14> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<15> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<16> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<17> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<18> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<19> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<20> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<21> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<22> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<23> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<24> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<25> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<26> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<27> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<28> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<29> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<30> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<31> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<32> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<33> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<34> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<35> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<36> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<37> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<38> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<39> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<40> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<41> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<42> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<43> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<44> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<45> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<46> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<47> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<48> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<49> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<50> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<51> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<52> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<53> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<54> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<55> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<56> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<57> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<58> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<59> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<60> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<61> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<62> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<63> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<64> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<65> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/test_patt_sel_GND_24_o_equal_15_o_mmx_out ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Result<1>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Result<0>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<4> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<5> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<6> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<7> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<8> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<9> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<10> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<11> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<12> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<13> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<14> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<15> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<16> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<17> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<18> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<19> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<20> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<21> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<22> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<23> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<24> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<25> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<26> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<27> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<28> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<29> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<30> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<31> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<32> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<33> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<34> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<35> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<36> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<37> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<38> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<39> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<40> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<41> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<42> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<43> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<44> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<45> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<46> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<47> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<48> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<49> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<50> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<51> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<52> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<53> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<54> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<55> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<56> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<57> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count[6]_reduce_and_6_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/reset_tx_test_en_OR_183_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/new_tx_test_seed_4087 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd1_4149 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd2_4150 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd3_4151 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd1-In ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd3-In ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<4> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<5> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<6> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<7> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<8> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<9> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<10> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<11> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<12> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<13> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<14> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<15> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<16> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<17> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<18> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<19> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<20> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<21> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<22> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<23> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<24> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<25> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<26> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<27> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<28> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<29> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<30> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<31> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<32> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<33> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<34> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<35> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<36> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<37> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<38> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<39> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<40> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<41> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<42> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<43> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<44> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<45> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<46> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<47> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<48> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<49> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<50> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<51> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<52> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<53> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<54> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<55> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<56> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<57> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<58> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<59> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<60> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<61> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<62> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<63> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<64> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<65> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_1_4221 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/signal_ok_reg_4222 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_6_4223 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_3_4226 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4227 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_cnt[6]_GND_26_o_mux_32_OUT411 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_cnt[6]_GND_26_o_mux_32_OUT22 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2-In2_4374 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt_xor<3>11_4375 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt4 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt3 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt2 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2_4393 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3_4394 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1-In_4395 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2-In ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3-In ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0142_inv ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0174_inv_4399 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt[4]_GND_26_o_MUX_394_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_int ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt[4]_GND_26_o_mux_33_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt[4]_GND_26_o_mux_33_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt[4]_GND_26_o_mux_33_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt[4]_GND_26_o_mux_33_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt[4]_GND_26_o_mux_33_OUT<4> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt[6]_GND_26_o_mux_32_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt[6]_GND_26_o_mux_32_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt[6]_GND_26_o_mux_32_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt[6]_GND_26_o_mux_32_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt[6]_GND_26_o_mux_32_OUT<4> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt[6]_GND_26_o_mux_32_OUT<5> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt[6]_GND_26_o_mux_32_OUT<6> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_194_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_4420 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/test_sh_4421 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1_4422 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state[2]_GND_26_o_Mux_27_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In11 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1-In1_4425 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mmux_timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT17 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<15> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<14>_4428 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<14> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<13>_4430 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<13> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<12>_4432 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<12> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<11>_4434 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<11> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<10>_4436 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<10> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<9>_4438 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<9> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<8>_4440 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<8> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<7>_4442 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<7> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<6>_4444 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<6> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<5>_4446 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<5> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<4>_4448 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<4> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<3>_4450 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<2>_4452 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<1>_4454 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<0>_4456 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mcount_ber_cnt4 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mcount_ber_cnt3 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mcount_ber_cnt2 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mcount_ber_cnt1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mcount_ber_cnt ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/_n0120_inv ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1-In ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2-In_4465 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/_n0099_inv ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<4> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<5> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<6> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<7> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<8> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<9> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<10> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<11> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<12> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<13> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<14> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<15> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_done_INV_125_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_test_sh_4485 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state[2]_GND_27_o_Mux_27_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state[2]_GND_27_o_Mux_25_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4510 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<4> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<5> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<6> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<7> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<8> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<9> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<10> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<11> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<12> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<13> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<14> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<15> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcount_block_count_xor<3>11 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<11>_4586 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<10>_4587 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<10>_4588 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<9>_4589 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<9>_4590 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<8>_4591 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<8>_4592 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<7>_4593 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<7>_4594 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<6>_4595 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<6>_4596 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<5>_4597 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<5>_4598 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<4>_4599 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<4>_4600 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<3>_4601 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<3>_4602 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<2>_4603 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<2>_4604 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<1>_4605 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<0>_4607 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<20>_4616 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<20> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<19>_4618 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<19> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<18>_4620 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<18> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<17>_4622 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<17> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<16>_4624 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<16> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<15>_4626 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<15> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<14>_4628 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<14> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<13>_4630 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<13> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<12>_4632 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<12> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<11>_4634 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<11> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<10>_4636 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<10> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<9>_4638 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<9> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<8>_4640 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<8> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<7>_4642 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<7> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<6>_4644 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<6> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<5>_4646 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<5> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<4>_4648 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<4> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<3>_4650 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<2>_4652 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<1>_4654 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<0>_4656 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/_n0062_inv_4665 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/expected_data[63]_inv_8_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/rx_66_enc[65]_expected_data[63]_not_equal_9_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/rx_66_enc[65]_expected_data[63]_not_equal_7_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/err_block_count_inc_in_GND_28_o_MUX_424_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/ignore_next_mismatch_4671 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT2721 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT5611 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT111_4674 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4675 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_315_o<7>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_GND_30_o_equal_102_o<6>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_GND_30_o_equal_104_o<6>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_PWR_32_o_equal_106_o<6>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_GND_30_o_equal_92_o<6>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_GND_30_o_equal_94_o<6>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_PWR_32_o_equal_96_o<6>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_GND_30_o_equal_82_o<6>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_GND_30_o_equal_84_o<6>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_PWR_32_o_equal_86_o<6>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_GND_30_o_equal_52_o<6>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_GND_30_o_equal_54_o<6>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_PWR_32_o_equal_56_o<6>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_GND_30_o_equal_42_o<6>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_GND_30_o_equal_44_o<6>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_PWR_32_o_equal_46_o<6>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_GND_30_o_equal_32_o<6>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_GND_30_o_equal_34_o<6>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_PWR_32_o_equal_36_o<6>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_GND_30_o_equal_62_o<6>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_GND_30_o_equal_64_o<6>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_66_o<6>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_GND_30_o_equal_75_o<6>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_PWR_32_o_equal_77_o<6>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_118_o1_4700 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_310_o<7>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_312_o<7>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_306_o<7>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_304_o<7>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_308_o<7>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_GND_30_o_mux_178_OUT31 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o31 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_GND_30_o_equal_72_o<6>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_o4[3]_AND_120_o2_4709 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o21 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<48>2 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<29>2 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<40>2 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<16>2_4714 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<24>3 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<56>3 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<39>3 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<10>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<56>2 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<24>2 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<39>2 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<40>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<48>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<7>2 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<24>1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c7[6]_mux_272_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c7[6]_mux_272_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c7[6]_mux_272_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c7[6]_mux_272_OUT<4> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c7[6]_mux_272_OUT<5> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c7[6]_mux_272_OUT<6> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c7[6]_mux_272_OUT<7> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c6[6]_mux_261_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c6[6]_mux_261_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c6[6]_mux_261_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c6[6]_mux_261_OUT<4> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c6[6]_mux_261_OUT<5> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c6[6]_mux_261_OUT<6> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c6[6]_mux_261_OUT<7> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c5[6]_mux_250_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c5[6]_mux_250_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c5[6]_mux_250_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c5[6]_mux_250_OUT<4> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c5[6]_mux_250_OUT<5> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c5[6]_mux_250_OUT<6> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c5[6]_mux_250_OUT<7> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c4[6]_mux_239_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c4[6]_mux_239_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c4[6]_mux_239_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c4[6]_mux_239_OUT<4> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c4[6]_mux_239_OUT<5> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c4[6]_mux_239_OUT<6> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c4[6]_mux_239_OUT<7> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c3[6]_mux_228_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c3[6]_mux_228_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c3[6]_mux_228_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c3[6]_mux_228_OUT<4> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c3[6]_mux_228_OUT<5> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c3[6]_mux_228_OUT<6> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c3[6]_mux_228_OUT<7> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c2[6]_mux_217_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c2[6]_mux_217_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c2[6]_mux_217_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c2[6]_mux_217_OUT<4> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c2[6]_mux_217_OUT<5> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c2[6]_mux_217_OUT<6> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c2[6]_mux_217_OUT<7> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c1[6]_mux_206_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c1[6]_mux_206_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c1[6]_mux_206_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c1[6]_mux_206_OUT<4> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c1[6]_mux_206_OUT<5> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c1[6]_mux_206_OUT<6> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c1[6]_mux_206_OUT<7> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c0[6]_mux_195_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c0[6]_mux_195_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c0[6]_mux_195_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c0[6]_mux_195_OUT<4> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c0[6]_mux_195_OUT<5> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c0[6]_mux_195_OUT<6> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c0[6]_mux_195_OUT<7> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/n0275 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_GND_30_o_equal_102_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_GND_30_o_equal_92_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_GND_30_o_equal_82_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_GND_30_o_equal_72_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_GND_30_o_equal_62_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_GND_30_o_equal_52_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_GND_30_o_equal_42_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_GND_30_o_equal_32_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/o0[3]_o0[3]_OR_331_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_118_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_valid_control[3]_AND_122_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_valid_control[7]_AND_124_o_4803 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_o4[3]_AND_120_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_301_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_311_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_310_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_315_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_314_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_313_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_312_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_309_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_308_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_307_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_306_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_305_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_303_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_302_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_GND_30_o_equal_103_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_PWR_32_o_equal_109_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_PWR_32_o_equal_108_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_PWR_32_o_equal_107_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_PWR_32_o_equal_106_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_GND_30_o_equal_93_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_PWR_32_o_equal_99_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_PWR_32_o_equal_98_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_PWR_32_o_equal_97_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_PWR_32_o_equal_96_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_GND_30_o_equal_83_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_PWR_32_o_equal_89_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_PWR_32_o_equal_88_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_PWR_32_o_equal_87_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_PWR_32_o_equal_86_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_GND_30_o_equal_73_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_GND_30_o_equal_75_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_GND_30_o_equal_74_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_PWR_32_o_equal_79_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_PWR_32_o_equal_78_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_PWR_32_o_equal_77_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_PWR_32_o_equal_76_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_GND_30_o_equal_63_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_69_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_68_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_67_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_66_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_GND_30_o_equal_53_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_PWR_32_o_equal_59_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_PWR_32_o_equal_58_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_PWR_32_o_equal_57_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_PWR_32_o_equal_56_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_GND_30_o_equal_43_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_PWR_32_o_equal_49_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_PWR_32_o_equal_48_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_PWR_32_o_equal_47_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_PWR_32_o_equal_46_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_GND_30_o_equal_33_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_PWR_32_o_equal_39_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_PWR_32_o_equal_38_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_PWR_32_o_equal_37_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_PWR_32_o_equal_36_o ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out[7]_GND_30_o_mux_323_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out[7]_GND_30_o_mux_323_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out[7]_GND_30_o_mux_323_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out[7]_GND_30_o_mux_323_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out[7]_GND_30_o_mux_323_OUT<4> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out[7]_GND_30_o_mux_323_OUT<5> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out[7]_GND_30_o_mux_323_OUT<6> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out[7]_GND_30_o_mux_323_OUT<7> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<4> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<5> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<6> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<7> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<8> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<9> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<10> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<11> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<12> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<13> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<14> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<15> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<16> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<17> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<18> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<19> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<20> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<21> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<22> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<23> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<24> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<25> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<26> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<27> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<28> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<29> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<30> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<31> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<32> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<33> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<34> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<35> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<36> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<37> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<38> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<39> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<40> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<41> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<42> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<43> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<44> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<45> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<46> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<47> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<48> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<49> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<50> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<51> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<52> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<53> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<54> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<55> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<56> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<57> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<58> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<59> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<60> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<61> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<62> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<63> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next_reg[2]_GND_30_o_mux_182_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next_reg[2]_GND_30_o_mux_182_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next_reg[2]_GND_30_o_mux_182_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg[2]_GND_30_o_mux_145_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg[2]_GND_30_o_mux_145_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg[2]_GND_30_o_mux_145_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1078 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_0_4941 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_1_4942 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_3_4943 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_4_4944 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_5_4945 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_6_4946 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_7_4947 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_0_4948 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_1_4949 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_3_4950 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_4_4951 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_5_4952 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_6_4953 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_7_4954 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_0_4955 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_1_4956 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_3_4957 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_4_4958 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_5_4959 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_6_4960 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_7_4961 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_0_4962 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_1_4963 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_3_4964 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_4_4965 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_5_4966 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_6_4967 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_7_4968 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_0_4969 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_1_4970 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_3_4971 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_4_4972 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_5_4973 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_6_4974 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_7_4975 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_0_4976 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_1_4977 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_3_4978 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_4_4979 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_5_4980 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_6_4981 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_7_4982 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_0_4983 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_1_4984 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_3_4985 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_4_4986 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_5_4987 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_6_4988 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_7_4989 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_0_4990 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_1_4991 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_3_4992 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_4_4993 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_5_4994 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_6_4995 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_7_4996 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1231_5064 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1102 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd1_5067 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2_5068 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5069 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd1-In_5070 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2-In_5071 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3-In ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT<4> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT<5> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT<6> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT<7> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<0> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<1> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<2> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<3> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<4> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<5> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<6> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<7> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<8> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<9> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<10> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<11> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<12> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<13> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<14> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<15> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<16> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<17> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<18> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<19> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<20> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<21> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<22> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<23> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<24> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<25> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<26> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<27> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<28> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<29> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<30> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<31> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<32> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<33> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<34> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<35> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<36> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<37> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<38> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<39> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<40> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<41> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<42> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<43> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<44> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<45> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<46> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<47> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<48> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<49> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<50> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<51> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<52> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<53> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<54> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<55> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<56> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<57> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<58> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<59> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<60> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<61> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<62> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<63> ;
  wire N2;
  wire N4;
  wire N6;
  wire N8;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2-In1_5153 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2-In2_5154 ;
  wire N10;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_PWR_65_o_not_equal_135_o1_5156 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_PWR_65_o_not_equal_135_o2_5157 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_PWR_65_o_not_equal_129_o1_5158 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_PWR_65_o_not_equal_129_o2_5159 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_PWR_65_o_not_equal_132_o1_5160 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_PWR_65_o_not_equal_132_o2_5161 ;
  wire N12;
  wire N14;
  wire N16;
  wire N18;
  wire N20;
  wire N22;
  wire N24;
  wire N26;
  wire N28;
  wire N30;
  wire N32;
  wire N34;
  wire N36;
  wire N38;
  wire N40;
  wire N42;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o<15> ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o<15>1_5179 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT91 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT92_5181 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT93_5182 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT94_5183 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT96 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT97_5185 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT98_5186 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT99_5187 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT3 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT31_5189 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT32_5190 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT33_5191 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT34_5192 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT35_5193 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT36_5194 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT37_5195 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT38_5196 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT13_5197 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT131_5198 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT132_5199 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT133_5200 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT134_5201 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT135_5202 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT136_5203 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT137_5204 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT14 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT141_5206 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT142_5207 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT143_5208 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT144_5209 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT145_5210 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT146_5211 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT147_5212 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT148_5213 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT111 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT112_5215 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT113_5216 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT114_5217 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT115_5218 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT116_5219 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT10 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT101_5221 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT102_5222 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT103_5223 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT104_5224 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT106 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT107_5226 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT108_5227 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT12_5228 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT122 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT123_5230 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT124_5231 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT125_5232 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT126_5233 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT127_5234 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT6 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT61_5236 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT62_5237 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT63_5238 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT64_5239 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT65_5240 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT15_5241 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT151_5242 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT152_5243 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT153_5244 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT154_5245 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT155_5246 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT156_5247 ;
  wire N44;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT41_5249 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT42_5250 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT43_5251 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT44_5252 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT45_5253 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT46_5254 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT16_5255 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT161_5256 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT162_5257 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT163_5258 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT164_5259 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT165_5260 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT166_5261 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT167_5262 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT5 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT51_5264 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT52_5265 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT53_5266 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT54_5267 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT55_5268 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT56_5269 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT7 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT71_5271 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT72_5272 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT73_5273 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT74_5274 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT75_5275 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT76_5276 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT2 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT21 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT22_5279 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT23_5280 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT24_5281 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT25_5282 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT26_5283 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT17_5285 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT18_5286 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT110_5287 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT117_5288 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT118_5289 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT119_5290 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT120_5291 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT128_5292 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT129_5293 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT8 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT82 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT83_5296 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT84_5297 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT85_5298 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT86_5299 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT87_5300 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT88_5301 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode11_5302 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode12_5303 ;
  wire N46;
  wire N48;
  wire N50;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o1_5307 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o2_5308 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o3_5309 ;
  wire N52;
  wire N54;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd2-In1_5312 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3-In1_5313 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3-In2_5314 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq<0>1_5315 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq<0>2_5316 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq<1>1_5317 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq<1>2_5318 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n08541_5319 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n08542_5320 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n08543_5321 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT8 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT81_5323 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT82_5324 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT83_5325 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT17 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT171_5327 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT173 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT175 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT14 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT141_5331 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT142_5332 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT145_5333 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1111 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11111_5335 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11112_5336 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11114 ;
  wire N58;
  wire N60;
  wire N62;
  wire N64;
  wire N66;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<1>1_5343 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<1>2_5344 ;
  wire N68;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<1>1_5346 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<1>2_5347 ;
  wire N70;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<1>1_5349 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<1>2_5350 ;
  wire N72;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<1>1_5352 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<1>2_5353 ;
  wire N74;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<1>1_5355 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<1>2_5356 ;
  wire N76;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<1>1_5358 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<1>2_5359 ;
  wire N78;
  wire N80;
  wire N82;
  wire N84;
  wire N86;
  wire N88;
  wire N90;
  wire N92;
  wire N94;
  wire N96;
  wire N98;
  wire N100;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT48 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT481_5373 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT53 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT531_5375 ;
  wire N102;
  wire N104;
  wire N106;
  wire N108;
  wire N110;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o1_5381 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o2_5382 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o7_5383 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o12_5384 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o17_5385 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code12 ;
  wire N112;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code5 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code51_5389 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code52_5390 ;
  wire N114;
  wire N116;
  wire N118;
  wire N120;
  wire N122;
  wire N124;
  wire N126;
  wire N128;
  wire N130;
  wire N132;
  wire N134;
  wire N136;
  wire N138;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>21_5404 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>22_5405 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT21 ;
  wire N140;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT5 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT51_5409 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT52_5410 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT53_5411 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT54_5412 ;
  wire N142;
  wire N144;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code8 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code81_5416 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code82_5417 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code72 ;
  wire N148;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code4 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code41_5421 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code42_5422 ;
  wire N150;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code3 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code31_5425 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code32_5426 ;
  wire N152;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code2 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code21_5429 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code22_5430 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<4>1_5431 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<5>1_5432 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<5>2_5433 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<6>1_5434 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<6>2_5435 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<5>1_5436 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<5>2_5437 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<3>1_5438 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<3>2_5439 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<6>1_5440 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<6>2_5441 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<5>1_5442 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<5>2_5443 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<3>1_5444 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<3>2_5445 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<6>1_5446 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<6>2_5447 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<5>1_5448 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<5>2_5449 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<3>1_5450 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<3>2_5451 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<6>1_5452 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<6>2_5453 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<5>1_5454 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<5>2_5455 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<3>1_5456 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<3>2_5457 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<6>1_5458 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<6>2_5459 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<5>1_5460 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<5>2_5461 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<3>1_5462 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<3>2_5463 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<6>1_5464 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<6>2_5465 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<3>1_5466 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<3>2_5467 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT117 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1171_5469 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1172_5470 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1173 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1175 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1176_5473 ;
  wire N154;
  wire N156;
  wire N158;
  wire N160;
  wire N166;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<4>1_5479 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<4>1_5480 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<4>1_5481 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<4>1_5482 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<4>1_5483 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT202 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT203_5485 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT204_5486 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out14111_5487 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out14112_5488 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out14113_5489 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out14114_5490 ;
  wire N168;
  wire N170;
  wire N172;
  wire N174;
  wire N176;
  wire N178;
  wire N180;
  wire N182;
  wire N184;
  wire N186;
  wire N188;
  wire N190;
  wire N192;
  wire N194;
  wire N196;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT111_5507 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT112_5508 ;
  wire N198;
  wire N200;
  wire N202;
  wire N204;
  wire N206;
  wire N214;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT9 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT8 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT7 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT6 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT5 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT58 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT57 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT56 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT55 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT54 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT45 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT4 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT34 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT32_5528 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT31_5529 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT3 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT30 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT29 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT28 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT27 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT26 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT25 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT24 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT23 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT22_5539 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT21_5540 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT2 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT20 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT19 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT18 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT17 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT16 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT15 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT14 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT13 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT12_5550 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT11_5551 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT10 ;
  wire N216;
  wire N218;
  wire N220;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2-In1_5557 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2-In3_5558 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2-In4_5559 ;
  wire N222;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3-In1_5561 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3-In2_5562 ;
  wire N224;
  wire N226;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In1_5565 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In2_5566 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In3_5567 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In4_5568 ;
  wire N228;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1-In2_5570 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/out ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/out1_5572 ;
  wire N230;
  wire N234;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT42_5575 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT41 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT40 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT39 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT38 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT35 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT36 ;
  wire N238;
  wire N240;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT33_5584 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT332_5585 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT27 ;
  wire N246;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT32 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT321_5589 ;
  wire N248;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT8 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT16 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT15 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT14 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT13 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT11 ;
  wire N250;
  wire N252;
  wire N254;
  wire N256;
  wire N258;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT51 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT50 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT49 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT48 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT47 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT43 ;
  wire N262;
  wire N264;
  wire N268;
  wire N272;
  wire N276;
  wire N278;
  wire N280;
  wire N282;
  wire N284;
  wire N286;
  wire N290;
  wire N292;
  wire N294;
  wire N296;
  wire N298;
  wire N300;
  wire N302;
  wire N304;
  wire N306;
  wire N308;
  wire N312;
  wire N314;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT611 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT612_5631 ;
  wire N320;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT621 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT622_5634 ;
  wire N324;
  wire N326;
  wire N328;
  wire N330;
  wire N332;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c4[6]_mux_239_OUT4 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c4[6]_mux_239_OUT41_5641 ;
  wire N334;
  wire N336;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_GND_30_o_mux_178_OUT312_5644 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o1_5645 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o2_5646 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o3_5647 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o4_5648 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o5_5649 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o6_5650 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o7_5651 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o8_5652 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o9_5653 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o10_5654 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o11_5655 ;
  wire N338;
  wire N340;
  wire N344;
  wire N346;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT9 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT44 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT18 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT17 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_118_o2_5664 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_118_o3_5665 ;
  wire N362;
  wire N364;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3-In1_5668 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3-In2_5669 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_next_state1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT163 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1631_5672 ;
  wire N366;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_glue_set_5674 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int_0_glue_set_5675 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int_6_glue_set_5676 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_1_glue_set_5677 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_3_glue_set_5678 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_2_glue_set_5679 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_1_glue_set_5680 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_3_glue_set_5681 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_2_glue_set_5682 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_1_glue_set_5683 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_3_glue_set_5684 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_2_glue_set_5685 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_7_glue_set_5686 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_6_glue_set_5687 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_5_glue_set_5688 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_4_glue_set_5689 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_3_glue_set_5690 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_2_glue_set_5691 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_1_glue_set_5692 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_0_glue_set_5693 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<14>_rt_5694 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<13>_rt_5695 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<12>_rt_5696 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<11>_rt_5697 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<10>_rt_5698 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<9>_rt_5699 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<8>_rt_5700 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<7>_rt_5701 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<6>_rt_5702 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<5>_rt_5703 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<4>_rt_5704 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<3>_rt_5705 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<2>_rt_5706 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<1>_rt_5707 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<14>_rt_5708 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<13>_rt_5709 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<12>_rt_5710 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<11>_rt_5711 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<10>_rt_5712 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<9>_rt_5713 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<8>_rt_5714 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<7>_rt_5715 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<6>_rt_5716 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<5>_rt_5717 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<4>_rt_5718 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<3>_rt_5719 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<2>_rt_5720 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<1>_rt_5721 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<14>_rt_5722 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<13>_rt_5723 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<12>_rt_5724 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<11>_rt_5725 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<10>_rt_5726 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<9>_rt_5727 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<8>_rt_5728 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<7>_rt_5729 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<6>_rt_5730 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<5>_rt_5731 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<4>_rt_5732 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<3>_rt_5733 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<2>_rt_5734 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<1>_rt_5735 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<14>_rt_5736 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<13>_rt_5737 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<12>_rt_5738 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<11>_rt_5739 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<10>_rt_5740 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<9>_rt_5741 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<8>_rt_5742 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<7>_rt_5743 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<6>_rt_5744 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<5>_rt_5745 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<4>_rt_5746 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<3>_rt_5747 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<2>_rt_5748 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<1>_rt_5749 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<6>_rt_5750 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<5>_rt_5751 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<4>_rt_5752 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<3>_rt_5753 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<2>_rt_5754 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<1>_rt_5755 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<0>_rt_5756 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_xor<15>_rt_5757 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_xor<15>_rt_5758 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_xor<15>_rt_5759 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_xor<15>_rt_5760 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_xor<7>_rt_5761 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_14/q_0_rstpot_5762 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_15/q_0_rstpot_5763 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15/q_0_rstpot_5764 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_rstpot_5765 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_9_0/q_0_rstpot_5766 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/empty_int_rstpot_5767 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_rstpot_5768 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/full_int_rstpot_5769 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/b_lock_rstpot_5770 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/hiber_rstpot_5771 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_slip_rstpot_5772 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_rx_link_up_core_reg_rstpot_5773 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_we_rising_rstpot_5774 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_rstpot_5775 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/indirect_read_rstpot_5776 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/read_enable_rstpot_5777 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd2_rstpot_5778 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd1_rstpot_5779 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/newedge_rstpot_5780 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/newedge_rstpot_5781 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/newedge_rstpot_5782 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/newedge_rstpot_5783 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/newedge_rstpot_5784 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/newedge_rstpot_5785 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/newedge_rstpot_5786 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/newedge_rstpot_5787 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/newedge_rstpot_5788 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/o4_0_rstpot_5789 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/o0_0_rstpot_5790 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/local_fault_rstpot_5791 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_sync_extra_rstpot_5792 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_sync_extra_rstpot_5793 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_sync_extra_rstpot_5794 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/ignore_next_mismatch_rstpot_5795 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/we_rstpot1_5796 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_8_11/q_0_rstpot1_5797 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_8_10/q_0_rstpot1_5798 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_1_2/q_0_rstpot1_5799 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_1_2/q_0_rstpot1_5800 ;
  wire N370;
  wire N372;
  wire N374;
  wire N376;
  wire N381;
  wire N382;
  wire N384;
  wire N388;
  wire N390;
  wire N392;
  wire N394;
  wire N400;
  wire N402;
  wire N404;
  wire N406;
  wire N408;
  wire N410;
  wire N414;
  wire N416;
  wire N418;
  wire N420;
  wire N422;
  wire N424;
  wire N426;
  wire N428;
  wire N430;
  wire N432;
  wire N434;
  wire N436;
  wire N438;
  wire N440;
  wire N442;
  wire N444;
  wire N446;
  wire N448;
  wire N450;
  wire N452;
  wire N454;
  wire N456;
  wire N458;
  wire N460;
  wire N462;
  wire N464;
  wire N466;
  wire N468;
  wire N470;
  wire N472;
  wire N474;
  wire N476;
  wire N478;
  wire N480;
  wire N482;
  wire N484;
  wire N486;
  wire N488;
  wire N490;
  wire N492;
  wire N494;
  wire N496;
  wire N500;
  wire N501;
  wire N503;
  wire N504;
  wire N506;
  wire N507;
  wire N513;
  wire N514;
  wire N516;
  wire N518;
  wire N520;
  wire N522;
  wire N523;
  wire N525;
  wire N527;
  wire N529;
  wire N530;
  wire N532;
  wire N533;
  wire N535;
  wire N537;
  wire N539;
  wire N541;
  wire N543;
  wire N545;
  wire N547;
  wire N548;
  wire N550;
  wire N551;
  wire N553;
  wire N554;
  wire N556;
  wire N558;
  wire N560;
  wire N562;
  wire N564;
  wire N566;
  wire N568;
  wire N570;
  wire N572;
  wire N574;
  wire N576;
  wire N578;
  wire N580;
  wire N582;
  wire N586;
  wire N588;
  wire N589;
  wire N590;
  wire N592;
  wire N594;
  wire N598;
  wire N600;
  wire N602;
  wire N604;
  wire N606;
  wire N612;
  wire N614;
  wire N616;
  wire N618;
  wire N620;
  wire N622;
  wire N624;
  wire N626;
  wire N628;
  wire N630;
  wire N632;
  wire N634;
  wire N636;
  wire N638;
  wire N640;
  wire N642;
  wire N644;
  wire N646;
  wire N648;
  wire N650;
  wire N652;
  wire N654;
  wire N656;
  wire N658;
  wire N660;
  wire N662;
  wire N664;
  wire N666;
  wire N668;
  wire N670;
  wire N672;
  wire N673;
  wire N674;
  wire N675;
  wire N676;
  wire N677;
  wire N678;
  wire N679;
  wire N680;
  wire N681;
  wire N682;
  wire N683;
  wire N684;
  wire N685;
  wire N686;
  wire N687;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mshreg_rd_addr2_1_5968 ;
  wire \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mshreg_rd_addr2_0_5969 ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[65].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[64].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[63].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[62].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[61].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[60].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[59].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[58].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[57].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[56].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[55].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[54].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[53].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[52].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[51].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[50].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[49].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[48].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[47].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[46].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[45].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[44].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[43].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[42].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[41].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[40].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[39].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[38].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[37].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[36].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[35].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[34].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[33].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[32].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[31].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[30].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[29].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[28].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[27].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[26].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[25].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[24].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[23].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[22].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[21].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[20].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[19].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[18].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[17].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[16].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[15].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[14].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[13].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[12].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[11].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[10].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[9].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[8].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[7].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[6].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[5].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[4].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[3].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[2].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[1].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[0].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[71].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[70].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[69].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[68].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[67].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[66].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[65].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[64].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[63].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[62].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[61].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[60].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[59].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[58].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[57].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[56].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[55].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[54].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[53].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[52].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[51].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[50].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[49].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[48].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[47].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[46].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[45].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[44].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[43].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[42].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[41].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[40].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[39].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[38].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[37].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[36].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[35].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[34].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[33].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[32].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[31].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[30].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[29].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[28].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[27].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[26].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[25].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[24].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[23].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[22].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[21].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[20].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[19].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[18].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[17].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[16].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[15].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[14].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[13].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[12].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[11].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[10].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[9].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[8].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[7].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[6].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[5].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[4].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[3].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[2].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[1].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[0].ram_i_SPO_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mshreg_rd_addr2_1_Q15_UNCONNECTED ;
  wire \NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mshreg_rd_addr2_0_Q15_UNCONNECTED ;
  wire [31 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd ;
  wire [7 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txc ;
  wire [65 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data ;
  wire [2 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type ;
  wire [65 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out ;
  wire [1 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txc_mux ;
  wire [65 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw ;
  wire [33 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt ;
  wire [65 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int ;
  wire [63 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data ;
  wire [7 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl ;
  wire [7 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/ctrl_out ;
  wire [63 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out ;
  wire [33 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt ;
  wire [6 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int ;
  wire [5 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q ;
  wire [15 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q ;
  wire [15 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q ;
  wire [15 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q ;
  wire [15 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q ;
  wire [9 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q ;
  wire [15 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q ;
  wire [15 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q ;
  wire [15 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q ;
  wire [9 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q ;
  wire [7 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg2 ;
  wire [7 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg ;
  wire [63 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 ;
  wire [63 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg ;
  wire [15 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count ;
  wire [7 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count ;
  wire [5 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count ;
  wire [15 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count ;
  wire [17 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q ;
  wire [3 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_all/q ;
  wire [15 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out ;
  wire [15 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q ;
  wire [15 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata ;
  wire [15 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count ;
  wire [17 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr ;
  wire [4 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad ;
  wire [15 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata ;
  wire [15 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg ;
  wire [15 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int ;
  wire [15 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int ;
  wire [15 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int ;
  wire [4 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count ;
  wire [0 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count_load_value ;
  wire [4 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg ;
  wire [1 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode ;
  wire [15 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured ;
  wire [20 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg ;
  wire [15 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q ;
  wire [15 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT ;
  wire [15 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q ;
  wire [7 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q ;
  wire [5 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/q ;
  wire [33 : 32] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q ;
  wire [15 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk ;
  wire [1 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 ;
  wire [33 : 32] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 ;
  wire [33 : 32] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 ;
  wire [33 : 32] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 ;
  wire [33 : 32] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 ;
  wire [17 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0 ;
  wire [17 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 ;
  wire [17 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 ;
  wire [17 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 ;
  wire [14 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy ;
  wire [0 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_lut ;
  wire [6 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy ;
  wire [0 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_lut ;
  wire [15 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result ;
  wire [5 : 1] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Result ;
  wire [65 : 2] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data ;
  wire [3 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray ;
  wire [3 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray ;
  wire [3 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Result ;
  wire [2 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/emuxcyo ;
  wire [2 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/fmuxcyo ;
  wire [3 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ecomp ;
  wire [3 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/fcomp ;
  wire [3 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_lastgray ;
  wire [3 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_gray ;
  wire [3 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_truegray ;
  wire [3 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_gray_rdclk ;
  wire [3 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_gray_rdclk0 ;
  wire [3 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_gray ;
  wire [3 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rag_writesync ;
  wire [3 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rag_writesync0 ;
  wire [3 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_lastgray_wrclk ;
  wire [3 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_lastgray_wrclk0 ;
  wire [65 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg ;
  wire [3 : 2] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/status ;
  wire [3 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr ;
  wire [3 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr ;
  wire [71 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data ;
  wire [7 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out ;
  wire [63 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out ;
  wire [2 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i0/comp ;
  wire [1 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i0/muxcyo ;
  wire [2 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i1/comp ;
  wire [1 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i1/muxcyo ;
  wire [1 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_seq_comb ;
  wire [1 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_idle_comb ;
  wire [1 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_seq ;
  wire [1 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_idle ;
  wire [63 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe ;
  wire [7 : 4] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_delay ;
  wire [63 : 32] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay ;
  wire [7 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe ;
  wire [7 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/muxcyo ;
  wire [8 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/comp ;
  wire [7 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/muxcyo ;
  wire [8 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/comp ;
  wire [3 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Result ;
  wire [2 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/emuxcyo ;
  wire [2 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/fmuxcyo ;
  wire [2 : 1] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ra_writesync ;
  wire [3 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ecomp ;
  wire [3 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/fcomp ;
  wire [3 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray ;
  wire [3 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_gray ;
  wire [3 : 1] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_nextgray ;
  wire [3 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_truegray ;
  wire [3 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray_rdclk ;
  wire [3 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray_rdclk0 ;
  wire [3 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray ;
  wire [3 : 1] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_nextgray ;
  wire [3 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe ;
  wire [3 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe1 ;
  wire [3 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe0 ;
  wire [3 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync ;
  wire [3 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync0 ;
  wire [3 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray_wrclk ;
  wire [3 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray_wrclk0 ;
  wire [71 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg ;
  wire [8 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/comp ;
  wire [7 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/muxcyo ;
  wire [8 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/comp ;
  wire [7 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/muxcyo ;
  wire [1 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq ;
  wire [1 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/is_idle ;
  wire [63 : 32] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay ;
  wire [7 : 4] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_delay ;
  wire [6 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT ;
  wire [6 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT ;
  wire [6 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT ;
  wire [6 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT ;
  wire [6 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT ;
  wire [6 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT ;
  wire [6 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_347_OUT ;
  wire [6 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_251_OUT ;
  wire [2 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/PWR_23_o_GND_22_o_mux_218_OUT ;
  wire [7 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d7 ;
  wire [6 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c7 ;
  wire [7 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d6 ;
  wire [6 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c6 ;
  wire [7 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d5 ;
  wire [6 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c5 ;
  wire [7 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d4 ;
  wire [0 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/o4 ;
  wire [6 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c4 ;
  wire [7 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d3 ;
  wire [6 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c3 ;
  wire [7 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d2 ;
  wire [6 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c2 ;
  wire [7 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d1 ;
  wire [6 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c1 ;
  wire [7 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d0 ;
  wire [0 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/o0 ;
  wire [6 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c0 ;
  wire [7 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field ;
  wire [2 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg ;
  wire [7 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg ;
  wire [7 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 ;
  wire [7 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 ;
  wire [63 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 ;
  wire [63 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 ;
  wire [6 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count ;
  wire [4 : 4] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mcount_block_count_cy ;
  wire [1 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel ;
  wire [0 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Maccum_tx_test_patt_seed_sel_lut ;
  wire [6 : 1] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Result ;
  wire [24 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb ;
  wire [57 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg ;
  wire [58 : 58] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/_n0043 ;
  wire [7 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out ;
  wire [63 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out ;
  wire [2 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next_reg ;
  wire [2 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg ;
  wire [65 : 2] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc ;
  wire [4 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt ;
  wire [6 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt ;
  wire [4 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt ;
  wire [4 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt ;
  wire [15 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us ;
  wire [57 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg ;
  wire [6 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count ;
  wire [6 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Result ;
  wire [0 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/expected_data ;
  wire [7 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control ;
  wire [65 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg ;
  wire [2 : 0] \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/next_state ;
  assign
    \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_5/d  = signal_detect,
    core_status[7] = NlwRenamedSig_OI_drp_dwe,
    core_status[6] = NlwRenamedSig_OI_drp_dwe,
    core_status[5] = NlwRenamedSig_OI_drp_dwe,
    core_status[4] = NlwRenamedSig_OI_drp_dwe,
    core_status[3] = NlwRenamedSig_OI_drp_dwe,
    core_status[2] = NlwRenamedSig_OI_drp_dwe,
    core_status[1] = NlwRenamedSig_OI_drp_dwe,
    core_status[0] = 
\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/q ,
    gt_txd[31] = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [31],
    gt_txd[30] = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [30],
    gt_txd[29] = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [29],
    gt_txd[28] = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [28],
    gt_txd[27] = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [27],
    gt_txd[26] = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [26],
    gt_txd[25] = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [25],
    gt_txd[24] = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [24],
    gt_txd[23] = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [23],
    gt_txd[22] = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [22],
    gt_txd[21] = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [21],
    gt_txd[20] = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [20],
    gt_txd[19] = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [19],
    gt_txd[18] = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [18],
    gt_txd[17] = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [17],
    gt_txd[16] = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [16],
    gt_txd[15] = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [15],
    gt_txd[14] = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [14],
    gt_txd[13] = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [13],
    gt_txd[12] = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [12],
    gt_txd[11] = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [11],
    gt_txd[10] = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [10],
    gt_txd[9] = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [9],
    gt_txd[8] = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [8],
    gt_txd[7] = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [7],
    gt_txd[6] = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [6],
    gt_txd[5] = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [5],
    gt_txd[4] = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [4],
    gt_txd[3] = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [3],
    gt_txd[2] = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [2],
    gt_txd[1] = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [1],
    gt_txd[0] = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [0],
    gt_txc[7] = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txc [7],
    gt_txc[6] = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txc [6],
    gt_txc[5] = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txc [5],
    gt_txc[4] = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txc [4],
    gt_txc[3] = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txc [3],
    gt_txc[2] = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txc [2],
    gt_txc[1] = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txc [1],
    gt_txc[0] = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txc [0],
    drp_daddr[15] = NlwRenamedSig_OI_drp_dwe,
    drp_daddr[14] = NlwRenamedSig_OI_drp_dwe,
    drp_daddr[13] = NlwRenamedSig_OI_drp_dwe,
    drp_daddr[12] = NlwRenamedSig_OI_drp_dwe,
    drp_daddr[11] = NlwRenamedSig_OI_drp_dwe,
    drp_daddr[10] = NlwRenamedSig_OI_drp_dwe,
    drp_daddr[9] = NlwRenamedSig_OI_drp_dwe,
    drp_daddr[8] = NlwRenamedSig_OI_drp_dwe,
    drp_daddr[7] = NlwRenamedSig_OI_drp_dwe,
    drp_daddr[6] = NlwRenamedSig_OI_drp_dwe,
    drp_daddr[5] = NlwRenamedSig_OI_drp_dwe,
    drp_daddr[4] = NlwRenamedSig_OI_drp_dwe,
    drp_daddr[3] = NlwRenamedSig_OI_drp_dwe,
    drp_daddr[2] = NlwRenamedSig_OI_drp_dwe,
    drp_daddr[1] = NlwRenamedSig_OI_drp_dwe,
    drp_daddr[0] = NlwRenamedSig_OI_drp_dwe,
    drp_di[15] = NlwRenamedSig_OI_drp_dwe,
    drp_di[14] = NlwRenamedSig_OI_drp_dwe,
    drp_di[13] = NlwRenamedSig_OI_drp_dwe,
    drp_di[12] = NlwRenamedSig_OI_drp_dwe,
    drp_di[11] = NlwRenamedSig_OI_drp_dwe,
    drp_di[10] = NlwRenamedSig_OI_drp_dwe,
    drp_di[9] = NlwRenamedSig_OI_drp_dwe,
    drp_di[8] = NlwRenamedSig_OI_drp_dwe,
    drp_di[7] = NlwRenamedSig_OI_drp_dwe,
    drp_di[6] = NlwRenamedSig_OI_drp_dwe,
    drp_di[5] = NlwRenamedSig_OI_drp_dwe,
    drp_di[4] = NlwRenamedSig_OI_drp_dwe,
    drp_di[3] = NlwRenamedSig_OI_drp_dwe,
    drp_di[2] = NlwRenamedSig_OI_drp_dwe,
    drp_di[1] = NlwRenamedSig_OI_drp_dwe,
    drp_di[0] = NlwRenamedSig_OI_drp_dwe,
    loopback_ctrl[2] = NlwRenamedSig_OI_drp_dwe,
    loopback_ctrl[1] = 
\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_0/q_0 ,
    loopback_ctrl[0] = NlwRenamedSig_OI_drp_dwe,
    pma_resetout = 
\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15/q_0 ,
    pcs_resetout = NlwRenamedSig_OI_pcs_resetout,
    mdio_out = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_out_259 ,
    mdio_tri = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_tri_260 ,
    gt_slip = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_slip_261 ,
    drp_den = NlwRenamedSig_OI_drp_dwe,
    drp_dwe = NlwRenamedSig_OI_drp_dwe,
    tx_disable = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_4/d2_262 ,
    tx_prbs31_en = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[0].synch_inst/q_263 ,
    rx_prbs31_en = \NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/q 
,
    clear_rx_prbs_err_count = \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clear_rx_prbs_err_count_265 ;
  VCC   XST_VCC (
    .P(N0)
  );
  GND   XST_GND (
    .G(NlwRenamedSig_OI_drp_dwe)
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resets_resyncs_i/resynch[0].synch_inst/q  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resets_resyncs_i/resynch[0].synch_inst/q_d1_MUX_807_o ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resets_resyncs_i/resynch[0].synch_inst/q_539 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resets_resyncs_i/resynch[0].synch_inst/d1  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resets_resyncs_i/resynch[0].synch_inst/d1_d_MUX_806_o ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resets_resyncs_i/resynch[0].synch_inst/q_d1_MUX_807_o )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/q  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/q_d1_MUX_807_o ),
    .Q(\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/q )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/d1  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/d1_d_MUX_806_o ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/d1_272 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/q  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/q_d1_MUX_807_o ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/q_543 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/d1  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/d1_d_MUX_806_o ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/d1_275 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/q  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/q_d1_MUX_807_o ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/q_542 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/d1  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/d1_d_MUX_806_o ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/d1_278 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/q  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/q_d1_MUX_807_o ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/q_541 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/d1  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/d1_281 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[0].synch_inst/q  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[0].synch_inst/q_d1_MUX_807_o ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[0].synch_inst/q_540 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[0].synch_inst/d1  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[0].synch_inst/d1_d_MUX_806_o ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[0].synch_inst/d1_284 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_d1_MUX_807_o ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_d1_MUX_807_o )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[0].synch_inst/q  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[0].synch_inst/q_d1_MUX_807_o ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[0].synch_inst/q_263 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[0].synch_inst/d1  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[0].synch_inst/d1_d_MUX_806_o ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[0].synch_inst/q_d1_MUX_807_o )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_806_o ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/q_d1_MUX_807_o )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/q  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/q_d1_MUX_807_o ),
    .Q(\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/q )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[1].synch_inst/d1  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[1].synch_inst/q_d1_MUX_807_o )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[1].synch_inst/q  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[1].synch_inst/q_d1_MUX_807_o ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[1].synch_inst/q_548 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[2].synch_inst/d1  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[2].synch_inst/d1_d_MUX_806_o ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[2].synch_inst/q_d1_MUX_807_o )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[2].synch_inst/q  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[2].synch_inst/q_d1_MUX_807_o ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[2].synch_inst/q_549 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_5/d1  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_5/d ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_5/d1_292 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_5/d2  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_5/d1_292 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_5/d2_550 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_4/d1  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_4/d ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_4/d1_293 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_4/d2  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_4/d1_293 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_4/d2_262 )
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local  (
    .C(clk156),
    .D(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 )
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rxreset_local  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_rxreset ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rxreset_local_430 )
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txc_7  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [6]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txc [7])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txc_6  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [5]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txc [6])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txc_5  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [4]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txc [5])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txc_4  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [3]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txc [4])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txc_3  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [2]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txc [3])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txc_2  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [1]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txc [2])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txc_1  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txc_mux [1]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txc [1])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txc_0  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txc_mux [0]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txc [0])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_31  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [33]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [31])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_30  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [32]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [30])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_29  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [31]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [29])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_28  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [30]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [28])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_27  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [29]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [27])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_26  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [28]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [26])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_25  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [27]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [25])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_24  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [26]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [24])
  );
  FDS   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_23  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [25]),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [23])
  );
  FDS   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_22  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [24]),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [22])
  );
  FDS   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_21  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [23]),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [21])
  );
  FDS   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_20  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [22]),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [20])
  );
  FDS   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_19  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [21]),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [19])
  );
  FDS   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_18  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [20]),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [18])
  );
  FDS   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_17  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [19]),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [17])
  );
  FDS   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_16  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [18]),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [16])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_15  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [17]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [15])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_14  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [16]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [14])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_13  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [15]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [13])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_12  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [14]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [12])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_11  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [13]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [11])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_10  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [12]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [10])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_9  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [11]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [9])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_8  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [10]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [8])
  );
  FDS   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_7  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [9]),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [7])
  );
  FDS   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_6  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [8]),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [6])
  );
  FDS   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_5  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [7]),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [5])
  );
  FDS   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_4  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [6]),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [4])
  );
  FDS   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_3  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [5]),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [3])
  );
  FDS   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_2  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [4]),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [2])
  );
  FDS   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_1  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [3]),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [1])
  );
  FDS   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd_0  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [2]),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txd [0])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_reset_core_reg  (
    .C(clk156),
    .D(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resets_resyncs_i/resynch[0].synch_inst/d1_d_MUX_806_o )
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/prbs31_tx_enable_core_reg  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/prbs31_tx_enable_core_int ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[0].synch_inst/d1_d_MUX_806_o )
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_slip_reg  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_slip_int_reg_499 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_slip_reg_502 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_slip_int_reg  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_555 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_slip_int_reg_499 )
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_test_mode_int_reg  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/q_543 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_test_mode_int_reg_501 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_65  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_65_764 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [65])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_64  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_64_763 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [64])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_63  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_63_762 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [63])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_62  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_62_761 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [62])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_61  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_61_760 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [61])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_60  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_60_759 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [60])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_59  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_59_758 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [59])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_58  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_58_757 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [58])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_57  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_57_756 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [57])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_56  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_56_755 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [56])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_55  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_55_754 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [55])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_54  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_54_753 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [54])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_53  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_53_752 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [53])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_52  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_52_751 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [52])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_51  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_51_750 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [51])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_50  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_50_749 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [50])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_49  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_49_748 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [49])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_48  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_48_747 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [48])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_47  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_47_746 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [47])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_46  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_46_745 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [46])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_45  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_45_744 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [45])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_44  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_44_743 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [44])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_43  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_43_742 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [43])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_42  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_42_741 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [42])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_41  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_41_740 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [41])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_40  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_40_739 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [40])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_39  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_39_738 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [39])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_38  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_38_737 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [38])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_37  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_37_736 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [37])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_36  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_36_735 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [36])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_35  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_35_734 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [35])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_34  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_34_733 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [34])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_33  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_33_732 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [33])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_32  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_32_731 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [32])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_31  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_31_730 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [31])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_30  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_30_729 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [30])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_29  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_29_728 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [29])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_28  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_28_727 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [28])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_27  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_27_726 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [27])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_26  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_26_725 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [26])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_25  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_25_724 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [25])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_24  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_24_723 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [24])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_23  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_23_722 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [23])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_22  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_22_721 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [22])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_21  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_21_720 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [21])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_20  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_20_719 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [20])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_19  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_19_718 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [19])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_18  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_18_717 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [18])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_17  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_17_716 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [17])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_16  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_16_715 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [16])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_15  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_15_714 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [15])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_14  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_14_713 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [14])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_13  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_13_712 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [13])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_12  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_12_711 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [12])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_11  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_11_710 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [11])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_10  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_10_709 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [10])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_9  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_9_708 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [9])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_8  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_8_707 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [8])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_7  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_7_706 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [7])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_6  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_6_705 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [6])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_5  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_5_704 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [5])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_4  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_4_703 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [4])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_3  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_3_702 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [3])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_2  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_2_701 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [2])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_1  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_1_700 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [1])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw_0  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_0_699 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [0])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clear_rx_prbs_err_count  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_test_mode_int_pcs_rxreset_AND_376_o ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clear_rx_prbs_err_count_265 )
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxdatavalid  (
    .C(rxusrclk2),
    .D(gt_rxc[2]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxdatavalid_504 )
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt_33  (
    .C(rxusrclk2),
    .D(gt_rxd[31]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [33])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt_32  (
    .C(rxusrclk2),
    .D(gt_rxd[30]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [32])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt_31  (
    .C(rxusrclk2),
    .D(gt_rxd[29]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [31])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt_30  (
    .C(rxusrclk2),
    .D(gt_rxd[28]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [30])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt_29  (
    .C(rxusrclk2),
    .D(gt_rxd[27]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [29])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt_28  (
    .C(rxusrclk2),
    .D(gt_rxd[26]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [28])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt_27  (
    .C(rxusrclk2),
    .D(gt_rxd[25]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [27])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt_26  (
    .C(rxusrclk2),
    .D(gt_rxd[24]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [26])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt_25  (
    .C(rxusrclk2),
    .D(gt_rxd[23]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [25])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt_24  (
    .C(rxusrclk2),
    .D(gt_rxd[22]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [24])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt_23  (
    .C(rxusrclk2),
    .D(gt_rxd[21]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [23])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt_22  (
    .C(rxusrclk2),
    .D(gt_rxd[20]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [22])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt_21  (
    .C(rxusrclk2),
    .D(gt_rxd[19]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [21])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt_20  (
    .C(rxusrclk2),
    .D(gt_rxd[18]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [20])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt_19  (
    .C(rxusrclk2),
    .D(gt_rxd[17]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [19])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt_18  (
    .C(rxusrclk2),
    .D(gt_rxd[16]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [18])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt_17  (
    .C(rxusrclk2),
    .D(gt_rxd[15]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [17])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt_16  (
    .C(rxusrclk2),
    .D(gt_rxd[14]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [16])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt_15  (
    .C(rxusrclk2),
    .D(gt_rxd[13]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [15])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt_14  (
    .C(rxusrclk2),
    .D(gt_rxd[12]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [14])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt_13  (
    .C(rxusrclk2),
    .D(gt_rxd[11]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [13])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt_12  (
    .C(rxusrclk2),
    .D(gt_rxd[10]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [12])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt_11  (
    .C(rxusrclk2),
    .D(gt_rxd[9]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [11])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt_10  (
    .C(rxusrclk2),
    .D(gt_rxd[8]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [10])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt_9  (
    .C(rxusrclk2),
    .D(gt_rxd[7]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [9])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt_8  (
    .C(rxusrclk2),
    .D(gt_rxd[6]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [8])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt_7  (
    .C(rxusrclk2),
    .D(gt_rxd[5]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [7])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt_6  (
    .C(rxusrclk2),
    .D(gt_rxd[4]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [6])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt_5  (
    .C(rxusrclk2),
    .D(gt_rxd[3]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [5])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt_4  (
    .C(rxusrclk2),
    .D(gt_rxd[2]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [4])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt_3  (
    .C(rxusrclk2),
    .D(gt_rxd[1]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [3])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt_2  (
    .C(rxusrclk2),
    .D(gt_rxd[0]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [2])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt_1  (
    .C(rxusrclk2),
    .D(gt_rxc[1]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [1])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt_0  (
    .C(rxusrclk2),
    .D(gt_rxc[0]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [0])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxheadervalid  (
    .C(rxusrclk2),
    .D(gt_rxc[3]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxheadervalid_503 )
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/prbs31_rx_enable_core_reg  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/prbs31_rx_enable_core_int ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/prbs31_rx_enable_core_reg_546 )
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clear_test_pattern_err_count_reg  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clear_test_pattern_err_count ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clear_test_pattern_err_count_reg_545 )
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_reset_clear_core_intr  (
    .C(clk156),
    .D(resetdone),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_reset_clear_core_intr_547 )
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg2_7  (
    .C(clk156),
    .D(xgmii_txc[7]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg2 [7])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg2_6  (
    .C(clk156),
    .D(xgmii_txc[6]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg2 [6])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg2_5  (
    .C(clk156),
    .D(xgmii_txc[5]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg2 [5])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg2_4  (
    .C(clk156),
    .D(xgmii_txc[4]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg2 [4])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg2_3  (
    .C(clk156),
    .D(xgmii_txc[3]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg2 [3])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg2_2  (
    .C(clk156),
    .D(xgmii_txc[2]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg2 [2])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg2_1  (
    .C(clk156),
    .D(xgmii_txc[1]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg2 [1])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg2_0  (
    .C(clk156),
    .D(xgmii_txc[0]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg2 [0])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_63  (
    .C(clk156),
    .D(xgmii_txd[63]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [63])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_62  (
    .C(clk156),
    .D(xgmii_txd[62]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [62])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_61  (
    .C(clk156),
    .D(xgmii_txd[61]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [61])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_60  (
    .C(clk156),
    .D(xgmii_txd[60]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [60])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_59  (
    .C(clk156),
    .D(xgmii_txd[59]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [59])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_58  (
    .C(clk156),
    .D(xgmii_txd[58]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [58])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_57  (
    .C(clk156),
    .D(xgmii_txd[57]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [57])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_56  (
    .C(clk156),
    .D(xgmii_txd[56]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [56])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_55  (
    .C(clk156),
    .D(xgmii_txd[55]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [55])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_54  (
    .C(clk156),
    .D(xgmii_txd[54]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [54])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_53  (
    .C(clk156),
    .D(xgmii_txd[53]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [53])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_52  (
    .C(clk156),
    .D(xgmii_txd[52]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [52])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_51  (
    .C(clk156),
    .D(xgmii_txd[51]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [51])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_50  (
    .C(clk156),
    .D(xgmii_txd[50]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [50])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_49  (
    .C(clk156),
    .D(xgmii_txd[49]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [49])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_48  (
    .C(clk156),
    .D(xgmii_txd[48]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [48])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_47  (
    .C(clk156),
    .D(xgmii_txd[47]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [47])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_46  (
    .C(clk156),
    .D(xgmii_txd[46]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [46])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_45  (
    .C(clk156),
    .D(xgmii_txd[45]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [45])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_44  (
    .C(clk156),
    .D(xgmii_txd[44]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [44])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_43  (
    .C(clk156),
    .D(xgmii_txd[43]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [43])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_42  (
    .C(clk156),
    .D(xgmii_txd[42]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [42])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_41  (
    .C(clk156),
    .D(xgmii_txd[41]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [41])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_40  (
    .C(clk156),
    .D(xgmii_txd[40]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [40])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_39  (
    .C(clk156),
    .D(xgmii_txd[39]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [39])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_38  (
    .C(clk156),
    .D(xgmii_txd[38]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [38])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_37  (
    .C(clk156),
    .D(xgmii_txd[37]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [37])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_36  (
    .C(clk156),
    .D(xgmii_txd[36]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [36])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_35  (
    .C(clk156),
    .D(xgmii_txd[35]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [35])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_34  (
    .C(clk156),
    .D(xgmii_txd[34]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [34])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_33  (
    .C(clk156),
    .D(xgmii_txd[33]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [33])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_32  (
    .C(clk156),
    .D(xgmii_txd[32]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [32])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_31  (
    .C(clk156),
    .D(xgmii_txd[31]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [31])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_30  (
    .C(clk156),
    .D(xgmii_txd[30]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [30])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_29  (
    .C(clk156),
    .D(xgmii_txd[29]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [29])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_28  (
    .C(clk156),
    .D(xgmii_txd[28]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [28])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_27  (
    .C(clk156),
    .D(xgmii_txd[27]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [27])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_26  (
    .C(clk156),
    .D(xgmii_txd[26]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [26])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_25  (
    .C(clk156),
    .D(xgmii_txd[25]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [25])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_24  (
    .C(clk156),
    .D(xgmii_txd[24]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [24])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_23  (
    .C(clk156),
    .D(xgmii_txd[23]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [23])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_22  (
    .C(clk156),
    .D(xgmii_txd[22]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [22])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_21  (
    .C(clk156),
    .D(xgmii_txd[21]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [21])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_20  (
    .C(clk156),
    .D(xgmii_txd[20]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [20])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_19  (
    .C(clk156),
    .D(xgmii_txd[19]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [19])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_18  (
    .C(clk156),
    .D(xgmii_txd[18]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [18])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_17  (
    .C(clk156),
    .D(xgmii_txd[17]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [17])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_16  (
    .C(clk156),
    .D(xgmii_txd[16]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [16])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_15  (
    .C(clk156),
    .D(xgmii_txd[15]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [15])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_14  (
    .C(clk156),
    .D(xgmii_txd[14]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [14])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_13  (
    .C(clk156),
    .D(xgmii_txd[13]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [13])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_12  (
    .C(clk156),
    .D(xgmii_txd[12]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [12])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_11  (
    .C(clk156),
    .D(xgmii_txd[11]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [11])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_10  (
    .C(clk156),
    .D(xgmii_txd[10]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [10])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_9  (
    .C(clk156),
    .D(xgmii_txd[9]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [9])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_8  (
    .C(clk156),
    .D(xgmii_txd[8]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [8])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_7  (
    .C(clk156),
    .D(xgmii_txd[7]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [7])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_6  (
    .C(clk156),
    .D(xgmii_txd[6]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [6])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_5  (
    .C(clk156),
    .D(xgmii_txd[5]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [5])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_4  (
    .C(clk156),
    .D(xgmii_txd[4]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [4])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_3  (
    .C(clk156),
    .D(xgmii_txd[3]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [3])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_2  (
    .C(clk156),
    .D(xgmii_txd[2]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [2])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_1  (
    .C(clk156),
    .D(xgmii_txd[1]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [1])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2_0  (
    .C(clk156),
    .D(xgmii_txd[0]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [0])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_63  (
    .C(clk156),
    .D(xgmii_txd[63]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [63])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_62  (
    .C(clk156),
    .D(xgmii_txd[62]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [62])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_61  (
    .C(clk156),
    .D(xgmii_txd[61]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [61])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_60  (
    .C(clk156),
    .D(xgmii_txd[60]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [60])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_59  (
    .C(clk156),
    .D(xgmii_txd[59]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [59])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_58  (
    .C(clk156),
    .D(xgmii_txd[58]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [58])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_57  (
    .C(clk156),
    .D(xgmii_txd[57]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [57])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_56  (
    .C(clk156),
    .D(xgmii_txd[56]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [56])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_55  (
    .C(clk156),
    .D(xgmii_txd[55]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [55])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_54  (
    .C(clk156),
    .D(xgmii_txd[54]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [54])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_53  (
    .C(clk156),
    .D(xgmii_txd[53]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [53])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_52  (
    .C(clk156),
    .D(xgmii_txd[52]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [52])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_51  (
    .C(clk156),
    .D(xgmii_txd[51]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [51])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_50  (
    .C(clk156),
    .D(xgmii_txd[50]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [50])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_49  (
    .C(clk156),
    .D(xgmii_txd[49]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [49])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_48  (
    .C(clk156),
    .D(xgmii_txd[48]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [48])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_47  (
    .C(clk156),
    .D(xgmii_txd[47]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [47])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_46  (
    .C(clk156),
    .D(xgmii_txd[46]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [46])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_45  (
    .C(clk156),
    .D(xgmii_txd[45]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [45])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_44  (
    .C(clk156),
    .D(xgmii_txd[44]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [44])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_43  (
    .C(clk156),
    .D(xgmii_txd[43]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [43])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_42  (
    .C(clk156),
    .D(xgmii_txd[42]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [42])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_41  (
    .C(clk156),
    .D(xgmii_txd[41]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [41])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_40  (
    .C(clk156),
    .D(xgmii_txd[40]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [40])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_39  (
    .C(clk156),
    .D(xgmii_txd[39]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [39])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_38  (
    .C(clk156),
    .D(xgmii_txd[38]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [38])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_37  (
    .C(clk156),
    .D(xgmii_txd[37]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [37])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_36  (
    .C(clk156),
    .D(xgmii_txd[36]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [36])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_35  (
    .C(clk156),
    .D(xgmii_txd[35]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [35])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_34  (
    .C(clk156),
    .D(xgmii_txd[34]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [34])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_33  (
    .C(clk156),
    .D(xgmii_txd[33]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [33])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_32  (
    .C(clk156),
    .D(xgmii_txd[32]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [32])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_31  (
    .C(clk156),
    .D(xgmii_txd[31]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [31])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_30  (
    .C(clk156),
    .D(xgmii_txd[30]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [30])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_29  (
    .C(clk156),
    .D(xgmii_txd[29]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [29])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_28  (
    .C(clk156),
    .D(xgmii_txd[28]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [28])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_27  (
    .C(clk156),
    .D(xgmii_txd[27]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [27])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_26  (
    .C(clk156),
    .D(xgmii_txd[26]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [26])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_25  (
    .C(clk156),
    .D(xgmii_txd[25]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [25])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_24  (
    .C(clk156),
    .D(xgmii_txd[24]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [24])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_23  (
    .C(clk156),
    .D(xgmii_txd[23]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [23])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_22  (
    .C(clk156),
    .D(xgmii_txd[22]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [22])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_21  (
    .C(clk156),
    .D(xgmii_txd[21]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [21])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_20  (
    .C(clk156),
    .D(xgmii_txd[20]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [20])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_19  (
    .C(clk156),
    .D(xgmii_txd[19]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [19])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_18  (
    .C(clk156),
    .D(xgmii_txd[18]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [18])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_17  (
    .C(clk156),
    .D(xgmii_txd[17]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [17])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_16  (
    .C(clk156),
    .D(xgmii_txd[16]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [16])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_15  (
    .C(clk156),
    .D(xgmii_txd[15]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [15])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_14  (
    .C(clk156),
    .D(xgmii_txd[14]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [14])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_13  (
    .C(clk156),
    .D(xgmii_txd[13]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [13])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_12  (
    .C(clk156),
    .D(xgmii_txd[12]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [12])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_11  (
    .C(clk156),
    .D(xgmii_txd[11]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [11])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_10  (
    .C(clk156),
    .D(xgmii_txd[10]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [10])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_9  (
    .C(clk156),
    .D(xgmii_txd[9]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [9])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_8  (
    .C(clk156),
    .D(xgmii_txd[8]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [8])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_7  (
    .C(clk156),
    .D(xgmii_txd[7]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [7])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_6  (
    .C(clk156),
    .D(xgmii_txd[6]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [6])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_5  (
    .C(clk156),
    .D(xgmii_txd[5]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [5])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_4  (
    .C(clk156),
    .D(xgmii_txd[4]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [4])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_3  (
    .C(clk156),
    .D(xgmii_txd[3]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [3])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_2  (
    .C(clk156),
    .D(xgmii_txd[2]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [2])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_1  (
    .C(clk156),
    .D(xgmii_txd[1]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [1])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg_0  (
    .C(clk156),
    .D(xgmii_txd[0]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [0])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg_7  (
    .C(clk156),
    .D(xgmii_txc[7]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg [7])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg_6  (
    .C(clk156),
    .D(xgmii_txc[6]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg [6])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg_5  (
    .C(clk156),
    .D(xgmii_txc[5]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg [5])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg_4  (
    .C(clk156),
    .D(xgmii_txc[4]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg [4])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg_3  (
    .C(clk156),
    .D(xgmii_txc[3]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg [3])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg_2  (
    .C(clk156),
    .D(xgmii_txc[2]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg [2])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg_1  (
    .C(clk156),
    .D(xgmii_txc[1]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg [1])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg_0  (
    .C(clk156),
    .D(xgmii_txc[0]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg [0])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count_15  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT<15> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count [15])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count_14  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT<14> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count [14])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count_13  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT<13> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count [13])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count_12  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT<12> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count [12])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count_11  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT<11> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count [11])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count_10  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT<10> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count [10])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count_9  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT<9> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count [9])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count_8  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT<8> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count [8])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count_7  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT<7> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count [7])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count_6  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT<6> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count [6])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count_5  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT<5> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count [5])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count_4  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT<4> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count [4])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count_3  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT<3> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count [3])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count_2  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT<2> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count [2])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count_1  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT<1> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count [1])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count_0  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT<0> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count [0])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_we_reg  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/we_1362 ),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_we_reg_1340 )
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_reg3  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_reg2_1344 ),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_reg3_1342 )
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_reg2  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_reg1_GND_62_o_MUX_766_o ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_reg2_1344 )
  );
  FDS   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_in_reg3  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_in_reg2_1337 ),
    .S(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_in_reg3_1336 )
  );
  FDS   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_in_reg2  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_in_reg1_1338 ),
    .S(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_in_reg2_1337 )
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_reg1  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_in_GND_62_o_MUX_765_o ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_reg1_1343 )
  );
  FDS   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_in_reg1  (
    .C(clk156),
    .D(mdio_in),
    .S(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_in_reg1_1338 )
  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_xor<15>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<14>_1441 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_xor<15>_rt_5757 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<15> )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_xor<14>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<13>_1442 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<14>_rt_5694 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<14> )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<14>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<13>_1442 )
,
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<14>_rt_5694 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<14>_1441 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_xor<13>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<12>_1443 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<13>_rt_5695 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<13> )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<13>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<12>_1443 )
,
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<13>_rt_5695 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<13>_1442 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_xor<12>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<11>_1444 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<12>_rt_5696 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<12> )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<12>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<11>_1444 )
,
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<12>_rt_5696 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<12>_1443 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_xor<11>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<10>_1445 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<11>_rt_5697 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<11> )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<11>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<10>_1445 )
,
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<11>_rt_5697 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<11>_1444 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_xor<10>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<9>_1446 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<10>_rt_5698 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<10> )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<10>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<9>_1446 )
,
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<10>_rt_5698 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<10>_1445 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_xor<9>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<8>_1447 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<9>_rt_5699 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<9> )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<9>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<8>_1447 )
,
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<9>_rt_5699 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<9>_1446 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_xor<8>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<7>_1448 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<8>_rt_5700 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<8> )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<8>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<7>_1448 )
,
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<8>_rt_5700 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<8>_1447 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_xor<7>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<6>_1449 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<7>_rt_5701 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<7> )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<7>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<6>_1449 )
,
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<7>_rt_5701 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<7>_1448 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_xor<6>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<5>_1450 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<6>_rt_5702 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<6> )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<6>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<5>_1450 )
,
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<6>_rt_5702 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<6>_1449 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_xor<5>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<4>_1451 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<5>_rt_5703 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<5> )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<5>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<4>_1451 )
,
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<5>_rt_5703 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<5>_1450 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_xor<4>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<3>_1452 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<4>_rt_5704 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<4> )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<4>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<3>_1452 )
,
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<4>_rt_5704 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<4>_1451 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_xor<3>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<2>_1453 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<3>_rt_5705 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<3> )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<3>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<2>_1453 )
,
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<3>_rt_5705 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<3>_1452 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_xor<2>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<1>_1454 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<2>_rt_5706 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<2> )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<2>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<1>_1454 )
,
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<2>_rt_5706 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<2>_1453 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_xor<1>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<0>_1455 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<1>_rt_5707 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<1> )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<1>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<0>_1455 )
,
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<1>_rt_5707 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<1>_1454 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_xor<0>  (
    .CI(NlwRenamedSig_OI_drp_dwe),
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_lut<0> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<0> )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<0>  (
    .CI(NlwRenamedSig_OI_drp_dwe),
    .DI(N0),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_lut<0> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<0>_1455 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_xor<15>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<14>_1457 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_xor<15>_rt_5758 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<15> )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_xor<14>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<13>_1458 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<14>_rt_5708 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<14> )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<14>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<13>_1458 )
,
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<14>_rt_5708 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<14>_1457 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_xor<13>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<12>_1459 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<13>_rt_5709 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<13> )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<13>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<12>_1459 )
,
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<13>_rt_5709 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<13>_1458 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_xor<12>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<11>_1460 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<12>_rt_5710 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<12> )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<12>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<11>_1460 )
,
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<12>_rt_5710 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<12>_1459 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_xor<11>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<10>_1461 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<11>_rt_5711 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<11> )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<11>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<10>_1461 )
,
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<11>_rt_5711 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<11>_1460 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_xor<10>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<9>_1462 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<10>_rt_5712 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<10> )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<10>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<9>_1462 )
,
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<10>_rt_5712 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<10>_1461 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_xor<9>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<8>_1463 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<9>_rt_5713 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<9> )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<9>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<8>_1463 )
,
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<9>_rt_5713 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<9>_1462 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_xor<8>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<7>_1464 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<8>_rt_5714 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<8> )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<8>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<7>_1464 )
,
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<8>_rt_5714 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<8>_1463 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_xor<7>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<6>_1465 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<7>_rt_5715 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<7> )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<7>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<6>_1465 )
,
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<7>_rt_5715 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<7>_1464 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_xor<6>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<5>_1466 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<6>_rt_5716 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<6> )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<6>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<5>_1466 )
,
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<6>_rt_5716 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<6>_1465 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_xor<5>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<4>_1467 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<5>_rt_5717 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<5> )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<5>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<4>_1467 )
,
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<5>_rt_5717 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<5>_1466 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_xor<4>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<3>_1468 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<4>_rt_5718 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<4> )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<4>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<3>_1468 )
,
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<4>_rt_5718 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<4>_1467 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_xor<3>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<2>_1469 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<3>_rt_5719 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<3> )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<3>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<2>_1469 )
,
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<3>_rt_5719 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<3>_1468 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_xor<2>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<1>_1470 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<2>_rt_5720 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<2> )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<2>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<1>_1470 )
,
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<2>_rt_5720 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<2>_1469 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_xor<1>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<0>_1471 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<1>_rt_5721 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<1> )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<1>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<0>_1471 )
,
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<1>_rt_5721 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<1>_1470 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_xor<0>  (
    .CI(NlwRenamedSig_OI_drp_dwe),
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_lut<0> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<0> )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<0>  (
    .CI(NlwRenamedSig_OI_drp_dwe),
    .DI(N0),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_lut<0> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<0>_1471 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_xor<15>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<14>_1473 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_xor<15>_rt_5759 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<15> )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_xor<14>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<13>_1474 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<14>_rt_5722 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<14> )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<14>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<13>_1474 )
,
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<14>_rt_5722 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<14>_1473 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_xor<13>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<12>_1475 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<13>_rt_5723 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<13> )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<13>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<12>_1475 )
,
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<13>_rt_5723 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<13>_1474 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_xor<12>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<11>_1476 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<12>_rt_5724 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<12> )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<12>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<11>_1476 )
,
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<12>_rt_5724 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<12>_1475 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_xor<11>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<10>_1477 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<11>_rt_5725 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<11> )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<11>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<10>_1477 )
,
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<11>_rt_5725 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<11>_1476 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_xor<10>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<9>_1478 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<10>_rt_5726 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<10> )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<10>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<9>_1478 )
,
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<10>_rt_5726 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<10>_1477 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_xor<9>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<8>_1479 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<9>_rt_5727 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<9> )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<9>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<8>_1479 )
,
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<9>_rt_5727 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<9>_1478 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_xor<8>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<7>_1480 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<8>_rt_5728 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<8> )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<8>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<7>_1480 )
,
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<8>_rt_5728 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<8>_1479 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_xor<7>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<6>_1481 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<7>_rt_5729 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<7> )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<7>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<6>_1481 )
,
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<7>_rt_5729 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<7>_1480 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_xor<6>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<5>_1482 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<6>_rt_5730 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<6> )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<6>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<5>_1482 )
,
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<6>_rt_5730 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<6>_1481 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_xor<5>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<4>_1483 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<5>_rt_5731 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<5> )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<5>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<4>_1483 )
,
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<5>_rt_5731 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<5>_1482 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_xor<4>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<3>_1484 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<4>_rt_5732 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<4> )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<4>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<3>_1484 )
,
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<4>_rt_5732 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<4>_1483 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_xor<3>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<2>_1485 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<3>_rt_5733 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<3> )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<3>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<2>_1485 )
,
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<3>_rt_5733 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<3>_1484 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_xor<2>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<1>_1486 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<2>_rt_5734 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<2> )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<2>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<1>_1486 )
,
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<2>_rt_5734 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<2>_1485 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_xor<1>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<0>_1487 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<1>_rt_5735 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<1> )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<1>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<0>_1487 )
,
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<1>_rt_5735 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<1>_1486 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_xor<0>  (
    .CI(NlwRenamedSig_OI_drp_dwe),
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_lut<0> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<0> )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<0>  (
    .CI(NlwRenamedSig_OI_drp_dwe),
    .DI(N0),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_lut<0> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<0>_1487 )

  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count_4  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0262_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mcount_bit_count_eqn_4_1489 )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count [4])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count_3  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0262_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mcount_bit_count_eqn_3 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count [3])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count_2  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0262_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mcount_bit_count_eqn_2 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count [2])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count_1  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0262_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mcount_bit_count_eqn_1 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count [1])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count_0  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0262_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mcount_bit_count_eqn_0 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count [0])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2-In ),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2_1496 )
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3-In ),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3_1497 )
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1-In_1499 ),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1_1495 )
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4-In_1502 ),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1498 )
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg_4  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_350_o )
,
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [3]),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [4])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg_3  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_350_o )
,
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [2]),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [3])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg_2  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_350_o )
,
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [1]),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [2])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg_1  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_350_o )
,
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [0]),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [1])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg_0  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_350_o )
,
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_in_reg_1632 ),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [0])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode_1  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_347_o_1631 )
,
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [1]),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode_0  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_347_o_1631 )
,
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [0]),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [0])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg_15  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0267_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<15> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [15])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg_14  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0267_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<14> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [14])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg_13  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0267_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<13> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [13])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg_12  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0267_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<12> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [12])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg_11  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0267_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<11> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [11])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg_10  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0267_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<10> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [10])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg_9  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0267_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<9> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [9])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg_8  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0267_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<8> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [8])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg_7  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0267_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<7> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [7])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg_6  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0267_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<6> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [6])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg_5  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0267_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<5> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [5])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg_4  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0267_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<4> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [4])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg_3  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0267_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<3> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [3])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg_2  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0267_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<2> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [2])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg_1  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0267_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<1> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [1])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg_0  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0267_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<0> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [0])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_just_rose  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_reg_1646 ),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_just_rose_1645 )
  );
  FDSE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_tri  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1341 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_tri_int ),
    .S(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_tri_260 )
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int_15  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o )
,
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<15> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [15])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int_14  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o )
,
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<14> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [14])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int_13  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o )
,
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<13> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [13])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int_12  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o )
,
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<12> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [12])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int_11  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o )
,
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<11> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [11])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int_10  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o )
,
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<10> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [10])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int_9  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o )
,
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<9> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [9])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int_8  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o )
,
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<8> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [8])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int_7  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o )
,
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<7> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [7])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int_6  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o )
,
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<6> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [6])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int_5  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o )
,
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<5> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [5])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int_4  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o )
,
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<4> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [4])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int_3  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o )
,
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<3> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [3])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int_2  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o )
,
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<2> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [2])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int_1  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o )
,
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<1> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [1])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int_0  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o )
,
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [0])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int_15  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o )
,
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<15> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [15])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int_14  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o )
,
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<14> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [14])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int_13  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o )
,
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<13> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [13])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int_12  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o )
,
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<12> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [12])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int_11  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o )
,
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<11> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [11])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int_10  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o )
,
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<10> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [10])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int_9  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o )
,
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<9> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [9])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int_8  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o )
,
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<8> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [8])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int_7  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o )
,
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<7> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [7])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int_6  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o )
,
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<6> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [6])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int_5  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o )
,
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<5> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [5])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int_4  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o )
,
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<4> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [4])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int_3  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o )
,
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<3> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [3])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int_2  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o )
,
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<2> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [2])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int_1  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o )
,
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<1> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [1])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int_0  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o )
,
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [0])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int_15  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o )
,
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<15> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [15])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int_14  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o )
,
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<14> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [14])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int_13  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o )
,
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<13> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [13])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int_12  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o )
,
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<12> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [12])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int_11  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o )
,
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<11> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [11])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int_10  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o )
,
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<10> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [10])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int_9  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o )
,
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<9> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [9])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int_8  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o )
,
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<8> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [8])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int_7  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o )
,
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<7> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [7])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int_6  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o )
,
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<6> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [6])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int_5  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o )
,
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<5> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [5])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int_4  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o )
,
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<4> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [4])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int_3  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o )
,
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<3> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [3])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int_2  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o )
,
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<2> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [2])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int_1  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o )
,
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<1> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [1])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int_0  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o )
,
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0> )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [0])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_out  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1341 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_out_int ),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_out_259 )
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_in_reg  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1341 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_in_reg3_1336 ),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_in_reg_1632 )
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_match  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad[4]_devad[4]_OR_530_o ),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_match_1644 )
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_just_rose_opcode[1]_AND_362_o )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1361 )
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_reg  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1341 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_reg_1646 )
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured_15  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0271_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [15]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0256 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [15])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured_14  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0271_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [14]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0256 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [14])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured_13  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0271_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [13]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0256 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [13])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured_12  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0271_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [12]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0256 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [12])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured_11  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0271_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [11]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0256 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [11])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured_10  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0271_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [10]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0256 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [10])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured_9  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0271_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [9]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0256 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [9])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured_8  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0271_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [8]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0256 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [8])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured_7  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0271_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [7]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0256 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [7])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured_6  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0271_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [6]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0256 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [6])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured_5  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0271_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [5]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0256 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [5])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured_4  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0271_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [4]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0256 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [4])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured_3  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0271_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [3]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0256 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [3])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured_2  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0271_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [2]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0256 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [2])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured_1  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0271_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [1]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0256 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [1])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured_0  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0271_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [0]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0256 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [0])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1-In1 ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_0 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 )
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2-In1 ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_0 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 )
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3-In ),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1673 )
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count_15  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_366_o )
,
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [15]),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count [15])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count_14  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_366_o )
,
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [14]),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count [14])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count_13  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_366_o )
,
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [13]),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count [13])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count_12  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_366_o )
,
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [12]),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count [12])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count_11  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_366_o )
,
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [11]),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count [11])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count_10  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_366_o )
,
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [10]),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count [10])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count_9  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_366_o )
,
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [9]),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count [9])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count_8  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_366_o )
,
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [8]),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count [8])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count_7  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_366_o )
,
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [7]),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count [7])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count_6  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_366_o )
,
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [6]),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count [6])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count_5  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_366_o )
,
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [5]),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count [5])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count_4  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_366_o )
,
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [4]),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count [4])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count_3  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_366_o )
,
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [3]),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count [3])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count_2  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_366_o )
,
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [2]),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count [2])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count_1  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_366_o )
,
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [1]),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count [1])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count_0  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_366_o )
,
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [0]),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count [0])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg_20  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [4]),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [20])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg_19  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [3]),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [19])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg_18  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [2]),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [18])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg_17  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [17]),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [17])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg_16  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [16]),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [16])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg_15  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [15]),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [15])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg_14  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [14]),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [14])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg_13  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [13]),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [13])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg_12  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [12]),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [12])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg_11  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [11]),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [11])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg_10  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [10]),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [10])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg_9  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [9]),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [9])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg_8  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [8]),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [8])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg_7  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [7]),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [7])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg_6  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [6]),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [6])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg_5  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [5]),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg_4  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [4]),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [4])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg_3  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [3]),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg_2  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [2]),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg_1  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [1]),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg_0  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [0]),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0])
  );
  FDSE #(
    .INIT ( 1'b1 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_all/q_0  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_we ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [0]),
    .S(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_all/q [0])
  );
  FDSE #(
    .INIT ( 1'b1 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_all/q_1  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_we ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [1]),
    .S(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_all/q [1])
  );
  FDSE #(
    .INIT ( 1'b1 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_all/q_2  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_we ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [2]),
    .S(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_all/q [2])
  );
  FDSE #(
    .INIT ( 1'b1 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_all/q_3  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_we ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [3]),
    .S(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_all/q [3])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q_0  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_we ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [0]),
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [0])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q_1  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_we ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [1]),
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q_2  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_we ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [2]),
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q_3  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_we ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [3]),
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q_4  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_we ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [4]),
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [4])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q_5  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_we ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [5]),
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [5])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q_0  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q[9]_d[9]_mux_3_OUT<0> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q [0])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q_1  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q[9]_d[9]_mux_3_OUT<1> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q [1])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q_2  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q[9]_d[9]_mux_3_OUT<2> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q [2])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q_3  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q[9]_d[9]_mux_3_OUT<3> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q [3])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q_4  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q[9]_d[9]_mux_3_OUT<4> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q [4])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q_5  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q[9]_d[9]_mux_3_OUT<5> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q [5])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q_6  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q[9]_d[9]_mux_3_OUT<6> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q [6])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q_7  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q[9]_d[9]_mux_3_OUT<7> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q [7])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q_8  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q[9]_d[9]_mux_3_OUT<8> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q [8])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q_9  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q[9]_d[9]_mux_3_OUT<9> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q [9])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q_0  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q[9]_d[9]_mux_3_OUT<0> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q [0])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q_1  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q[9]_d[9]_mux_3_OUT<1> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q [1])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q_2  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q[9]_d[9]_mux_3_OUT<2> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q [2])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q_3  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q[9]_d[9]_mux_3_OUT<3> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q [3])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q_4  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q[9]_d[9]_mux_3_OUT<4> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q [4])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q_5  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q[9]_d[9]_mux_3_OUT<5> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q [5])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q_6  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q[9]_d[9]_mux_3_OUT<6> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q [6])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q_7  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q[9]_d[9]_mux_3_OUT<7> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q [7])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q_8  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q[9]_d[9]_mux_3_OUT<8> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q [8])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q_9  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q[9]_d[9]_mux_3_OUT<9> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q [9])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_32_12/q_0  (
    .C(clk156),
    .CE(N0),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[2].synch_inst/q_549 ),
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_32_12/q_0_1956 )
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_32_1/q_0  (
    .C(clk156),
    .CE(N0),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[1].synch_inst/q_548 ),
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_32_1/q_0_1955 )
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_32_0/q_0  (
    .C(clk156),
    .CE(N0),
    .D(\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/q ),
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_32_0/q_0_1954 )
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_8_10/re_prev  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_8_re ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_8_10/re_prev_1753 )
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_8_10/re_prev  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_8_re ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_8_10/re_prev_1754 )
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_1_2/re_prev  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_1_re ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_1_2/re_prev_1756 )
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_1_2/re_prev  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_1_re ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_1_2/re_prev_1757 )
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_15/re_prev  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_re ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_15/re_prev_1998 )
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_0/q_0  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_0/q[0]_d[0]_MUX_691_o ),
    .R
(\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15/q_0 ),
    .Q
(\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_0/q_0 )
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_11/q_0  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_11/q[0]_d[0]_MUX_691_o ),
    .R
(\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15/q_0 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_11/q_0_1251 )
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_11/q_0  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_11/q[0]_d[0]_MUX_691_o ),
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_11/q_0_1250 )
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_14/q_0  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_14/q[0]_d[0]_MUX_691_o ),
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o )
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q_0  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<0> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q [0])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q_1  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<1> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q [1])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q_2  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<2> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q [2])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q_3  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<3> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q [3])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q_4  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<4> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q [4])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q_5  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<5> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q [5])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q_6  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<6> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q [6])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q_7  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<7> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q [7])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q_8  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<8> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q [8])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q_9  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<9> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q [9])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q_10  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<10> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q [10])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q_11  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<11> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q [11])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q_12  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<12> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q [12])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q_13  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<13> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q [13])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q_14  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<14> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q [14])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q_15  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<15> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q [15])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q_0  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<0> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q [0])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q_1  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<1> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q [1])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q_2  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<2> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q [2])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q_3  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<3> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q [3])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q_4  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<4> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q [4])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q_5  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<5> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q [5])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q_6  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<6> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q [6])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q_7  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<7> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q [7])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q_8  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<8> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q [8])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q_9  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<9> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q [9])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q_10  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<10> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q [10])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q_11  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<11> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q [11])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q_12  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<12> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q [12])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q_13  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<13> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q [13])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q_14  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<14> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q [14])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q_15  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<15> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q [15])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q_0  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<0> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [0])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q_1  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<1> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [1])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q_2  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<2> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [2])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q_3  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<3> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [3])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q_4  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<4> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [4])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q_5  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<5> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [5])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q_6  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<6> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [6])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q_7  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<7> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [7])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q_8  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<8> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [8])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q_9  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<9> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [9])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q_10  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<10> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [10])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q_11  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<11> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [11])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q_12  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<12> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [12])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q_13  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<13> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [13])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q_14  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<14> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [14])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q_15  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<15> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [15])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q_0  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q[15]_d[15]_mux_3_OUT<0> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [0])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q_1  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q[15]_d[15]_mux_3_OUT<1> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [1])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q_2  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q[15]_d[15]_mux_3_OUT<2> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [2])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q_3  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q[15]_d[15]_mux_3_OUT<3> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [3])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q_4  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q[15]_d[15]_mux_3_OUT<4> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [4])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q_5  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q[15]_d[15]_mux_3_OUT<5> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [5])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q_6  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q[15]_d[15]_mux_3_OUT<6> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [6])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q_7  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q[15]_d[15]_mux_3_OUT<7> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [7])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q_8  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q[15]_d[15]_mux_3_OUT<8> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [8])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q_9  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q[15]_d[15]_mux_3_OUT<9> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [9])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q_10  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q[15]_d[15]_mux_3_OUT<10> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [10])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q_11  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q[15]_d[15]_mux_3_OUT<11> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [11])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q_12  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q[15]_d[15]_mux_3_OUT<12> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [12])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q_13  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q[15]_d[15]_mux_3_OUT<13> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [13])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q_14  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q[15]_d[15]_mux_3_OUT<14> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [14])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q_15  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q[15]_d[15]_mux_3_OUT<15> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [15])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q_0  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q[15]_d[15]_mux_3_OUT<0> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [0])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q_1  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q[15]_d[15]_mux_3_OUT<1> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [1])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q_2  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q[15]_d[15]_mux_3_OUT<2> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [2])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q_3  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q[15]_d[15]_mux_3_OUT<3> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [3])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q_4  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q[15]_d[15]_mux_3_OUT<4> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [4])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q_5  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q[15]_d[15]_mux_3_OUT<5> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [5])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q_6  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q[15]_d[15]_mux_3_OUT<6> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [6])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q_7  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q[15]_d[15]_mux_3_OUT<7> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [7])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q_8  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q[15]_d[15]_mux_3_OUT<8> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [8])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q_9  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q[15]_d[15]_mux_3_OUT<9> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [9])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q_10  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q[15]_d[15]_mux_3_OUT<10> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [10])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q_11  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q[15]_d[15]_mux_3_OUT<11> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [11])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q_12  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q[15]_d[15]_mux_3_OUT<12> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [12])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q_13  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q[15]_d[15]_mux_3_OUT<13> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [13])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q_14  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q[15]_d[15]_mux_3_OUT<14> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [14])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q_15  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q[15]_d[15]_mux_3_OUT<15> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [15])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q_0  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<0> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [0])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q_1  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<1> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [1])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q_2  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<2> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [2])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q_3  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<3> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [3])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q_4  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<4> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [4])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q_5  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<5> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [5])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q_6  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<6> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [6])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q_7  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<7> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [7])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q_8  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<8> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [8])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q_9  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<9> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [9])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q_10  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<10> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [10])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q_11  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<11> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [11])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q_12  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<12> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [12])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q_13  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<13> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [13])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q_14  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<14> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [14])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q_15  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<15> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [15])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q_0  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q[15]_d[15]_mux_3_OUT<0> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [0])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q_1  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q[15]_d[15]_mux_3_OUT<1> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [1])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q_2  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q[15]_d[15]_mux_3_OUT<2> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [2])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q_3  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q[15]_d[15]_mux_3_OUT<3> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [3])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q_4  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q[15]_d[15]_mux_3_OUT<4> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [4])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q_5  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q[15]_d[15]_mux_3_OUT<5> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [5])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q_6  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q[15]_d[15]_mux_3_OUT<6> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [6])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q_7  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q[15]_d[15]_mux_3_OUT<7> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [7])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q_8  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q[15]_d[15]_mux_3_OUT<8> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [8])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q_9  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q[15]_d[15]_mux_3_OUT<9> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [9])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q_10  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q[15]_d[15]_mux_3_OUT<10> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [10])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q_11  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q[15]_d[15]_mux_3_OUT<11> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [11])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q_12  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q[15]_d[15]_mux_3_OUT<12> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [12])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q_13  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q[15]_d[15]_mux_3_OUT<13> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [13])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q_14  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q[15]_d[15]_mux_3_OUT<14> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [14])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q_15  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q[15]_d[15]_mux_3_OUT<15> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [15])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q_0  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<0> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [0])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q_1  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<1> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [1])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q_2  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<2> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [2])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q_3  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<3> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [3])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q_4  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<4> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [4])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q_5  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<5> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [5])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q_6  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<6> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [6])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q_7  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<7> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [7])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q_8  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<8> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [8])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q_9  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<9> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [9])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q_10  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<10> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [10])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q_11  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<11> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [11])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q_12  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<12> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [12])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q_13  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<13> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [13])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q_14  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<14> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [14])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q_15  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<15> )
,
    .R(NlwRenamedSig_OI_pcs_resetout),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [15])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out_15  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [15]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rnw_inv ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out [15])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out_14  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [14]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rnw_inv ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out [14])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out_13  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [13]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rnw_inv ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out [13])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out_12  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [12]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rnw_inv ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out [12])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out_11  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [11]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rnw_inv ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out [11])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out_10  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [10]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rnw_inv ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out [10])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out_9  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [9]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rnw_inv ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out [9])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out_8  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [8]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rnw_inv ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out [8])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out_7  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [7]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rnw_inv ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out [7])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out_6  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [6]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rnw_inv ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out [6])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out_5  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [5]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rnw_inv ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out [5])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out_4  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [4]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rnw_inv ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out [4])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out_3  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [3]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rnw_inv ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out [3])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out_2  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [2]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rnw_inv ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out [2])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out_1  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [1]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rnw_inv ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out [1])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out_0  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [0]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rnw_inv ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out [0])
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/wrack  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/wrack_cs_AND_303_o ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/wrack_1244 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rdack  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rdack_rdack_OR_520_o ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rdack_1245 )
  );
  FDR #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/q_5  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/q[5]_GND_50_o_mux_3_OUT<5> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/re_rising ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/q [5])
  );
  FDR #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/q_4  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/q[5]_GND_50_o_mux_3_OUT<4> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/re_rising ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/q [4])
  );
  FDR #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/q_3  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/q[5]_GND_50_o_mux_3_OUT<3> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/re_rising ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/q [3])
  );
  FDR #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/q_2  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/q[5]_GND_50_o_mux_3_OUT<2> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/re_rising ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/q [2])
  );
  FDR #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/q_1  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/q[5]_GND_50_o_mux_3_OUT<1> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/re_rising ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/q [1])
  );
  FDR #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/q_0  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/q[5]_GND_50_o_mux_3_OUT<0> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/re_rising ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/q [0])
  );
  FDR #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q_7  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q[7]_GND_51_o_mux_3_OUT<7> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/re_rising ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q [7])
  );
  FDR #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q_6  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q[7]_GND_51_o_mux_3_OUT<6> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/re_rising ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q [6])
  );
  FDR #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q_5  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q[7]_GND_51_o_mux_3_OUT<5> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/re_rising ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q [5])
  );
  FDR #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q_4  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q[7]_GND_51_o_mux_3_OUT<4> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/re_rising ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q [4])
  );
  FDR #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q_3  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q[7]_GND_51_o_mux_3_OUT<3> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/re_rising ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q [3])
  );
  FDR #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q_2  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q[7]_GND_51_o_mux_3_OUT<2> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/re_rising ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q [2])
  );
  FDR #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q_1  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q[7]_GND_51_o_mux_3_OUT<1> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/re_rising ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q [1])
  );
  FDR #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q_0  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q[7]_GND_51_o_mux_3_OUT<0> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/re_rising ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q [0])
  );
  FDR #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q_15  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q[15]_GND_55_o_mux_3_OUT<15> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/re_rising ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q [15])
  );
  FDR #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q_14  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q[15]_GND_55_o_mux_3_OUT<14> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/re_rising ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q [14])
  );
  FDR #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q_13  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q[15]_GND_55_o_mux_3_OUT<13> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/re_rising ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q [13])
  );
  FDR #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q_12  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q[15]_GND_55_o_mux_3_OUT<12> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/re_rising ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q [12])
  );
  FDR #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q_11  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q[15]_GND_55_o_mux_3_OUT<11> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/re_rising ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q [11])
  );
  FDR #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q_10  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q[15]_GND_55_o_mux_3_OUT<10> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/re_rising ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q [10])
  );
  FDR #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q_9  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q[15]_GND_55_o_mux_3_OUT<9> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/re_rising ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q [9])
  );
  FDR #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q_8  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q[15]_GND_55_o_mux_3_OUT<8> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/re_rising ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q [8])
  );
  FDR #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q_7  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q[15]_GND_55_o_mux_3_OUT<7> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/re_rising ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q [7])
  );
  FDR #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q_6  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q[15]_GND_55_o_mux_3_OUT<6> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/re_rising ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q [6])
  );
  FDR #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q_5  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q[15]_GND_55_o_mux_3_OUT<5> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/re_rising ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q [5])
  );
  FDR #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q_4  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q[15]_GND_55_o_mux_3_OUT<4> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/re_rising ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q [4])
  );
  FDR #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q_3  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q[15]_GND_55_o_mux_3_OUT<3> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/re_rising ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q [3])
  );
  FDR #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q_2  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q[15]_GND_55_o_mux_3_OUT<2> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/re_rising ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q [2])
  );
  FDR #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q_1  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q[15]_GND_55_o_mux_3_OUT<1> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/re_rising ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q [1])
  );
  FDR #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q_0  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q[15]_GND_55_o_mux_3_OUT<0> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/re_rising ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q [0])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/re_prev  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_re ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/re_prev_2014 )
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q_15  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/_n0012_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<15> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [15])
  );
  FDE #(
    .INIT ( 1'b1 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q_14  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/_n0012_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<14> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [14])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q_13  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/_n0012_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<13> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [13])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q_12  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/_n0012_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<12> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [12])
  );
  FDE #(
    .INIT ( 1'b1 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q_11  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/_n0012_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<11> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [11])
  );
  FDE #(
    .INIT ( 1'b1 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q_10  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/_n0012_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<10> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [10])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q_9  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/_n0012_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<9> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [9])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q_8  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/_n0012_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<8> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [8])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q_7  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/_n0012_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<7> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [7])
  );
  FDE #(
    .INIT ( 1'b1 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q_6  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/_n0012_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<6> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [6])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q_5  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/_n0012_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<5> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [5])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q_4  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/_n0012_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<4> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [4])
  );
  FDE #(
    .INIT ( 1'b1 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q_3  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/_n0012_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<3> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [3])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q_2  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/_n0012_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<2> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [2])
  );
  FDE #(
    .INIT ( 1'b1 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q_1  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/_n0012_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<1> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [1])
  );
  FDE #(
    .INIT ( 1'b1 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q_0  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/_n0012_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<0> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [0])
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2-In ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2079 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1-In ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2080 )
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q_33  (
    .C(dclk),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<33> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [33])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q_32  (
    .C(dclk),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<32> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [32])
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_INV_322_o ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2081 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0_33  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0071_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_cs ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [33])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0_32  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0071_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_rnw ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [32])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3_33  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0063_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_cs ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [33])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3_32  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0063_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_rnw ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [32])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2_33  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0059_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_cs ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [33])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2_32  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0059_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_rnw ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [32])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1_33  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0067_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_cs ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [33])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1_32  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0067_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_rnw ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [32])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q_17  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2081 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<17> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [17])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q_16  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2081 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<16> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [16])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q_15  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2081 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<15> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [15])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q_14  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2081 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<14> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [14])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q_13  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2081 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<13> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [13])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q_12  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2081 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<12> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [12])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q_11  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2081 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<11> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [11])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q_10  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2081 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<10> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [10])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q_9  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2081 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<9> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [9])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q_8  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2081 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<8> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [8])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q_7  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2081 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<7> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [7])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q_6  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2081 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<6> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [6])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q_5  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2081 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<5> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [5])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q_4  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2081 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<4> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [4])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q_3  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2081 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<3> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [3])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q_2  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2081 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<2> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [2])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q_1  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2081 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<1> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [1])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q_0  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2081 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<0> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [0])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0_17  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0037 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_wrack_dclk ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0 [17])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0_16  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0037 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rdack_dclk ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0 [16])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0_15  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0037 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [15]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0 [15])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0_14  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0037 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [14]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0 [14])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0_13  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0037 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [13]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0 [13])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0_12  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0037 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [12]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0 [12])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0_11  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0037 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [11]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0 [11])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0_10  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0037 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [10]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0 [10])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0_9  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0037 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [9]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0 [9])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0_8  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0037 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [8]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0 [8])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0_7  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0037 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [7]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0 [7])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0_6  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0037 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [6]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0 [6])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0_5  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0037 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [5]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0 [5])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0_4  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0037 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [4]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0 [4])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0_3  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0037 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [3]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0 [3])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0_2  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0037 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [2]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0 [2])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0_1  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0037 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [1]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0 [1])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0_0  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0037 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [0]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0 [0])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3_17  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0040 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_wrack_dclk ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 [17])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3_16  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0040 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rdack_dclk ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 [16])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3_15  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0040 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [15]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 [15])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3_14  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0040 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [14]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 [14])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3_13  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0040 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [13]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 [13])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3_12  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0040 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [12]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 [12])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3_11  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0040 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [11]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 [11])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3_10  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0040 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [10]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 [10])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3_9  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0040 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [9]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 [9])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3_8  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0040 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [8]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 [8])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3_7  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0040 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [7]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 [7])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3_6  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0040 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [6]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 [6])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3_5  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0040 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [5]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 [5])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3_4  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0040 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [4]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 [4])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3_3  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0040 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [3]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 [3])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3_2  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0040 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [2]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 [2])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3_1  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0040 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [1]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 [1])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3_0  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0040 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [0]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 [0])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2_17  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0045 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_wrack_dclk ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 [17])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2_16  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0045 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rdack_dclk ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 [16])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2_15  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0045 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [15]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 [15])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2_14  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0045 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [14]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 [14])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2_13  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0045 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [13]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 [13])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2_12  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0045 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [12]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 [12])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2_11  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0045 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [11]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 [11])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2_10  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0045 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [10]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 [10])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2_9  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0045 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [9]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 [9])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2_8  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0045 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [8]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 [8])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2_7  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0045 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [7]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 [7])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2_6  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0045 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [6]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 [6])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2_5  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0045 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [5]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 [5])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2_4  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0045 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [4]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 [4])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2_3  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0045 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [3]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 [3])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2_2  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0045 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [2]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 [2])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2_1  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0045 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [1]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 [1])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2_0  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0045 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [0]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 [0])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1_17  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0043 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_wrack_dclk ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 [17])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1_16  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0043 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rdack_dclk ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 [16])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1_15  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0043 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [15]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 [15])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1_14  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0043 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [14]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 [14])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1_13  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0043 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [13]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 [13])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1_12  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0043 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [12]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 [12])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1_11  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0043 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [11]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 [11])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1_10  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0043 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [10]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 [10])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1_9  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0043 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [9]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 [9])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1_8  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0043 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [8]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 [8])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1_7  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0043 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [7]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 [7])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1_6  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0043 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [6]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 [6])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1_5  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0043 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [5]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 [5])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1_4  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0043 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [4]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 [4])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1_3  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0043 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [3]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 [3])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1_2  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0043 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [2]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 [2])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1_1  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0043 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [1]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 [1])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1_0  (
    .C(dclk),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0043 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [0]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 [0])
  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_xor<15>  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [14]),
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_xor<15>_rt_5760 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [15])
  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_xor<14>  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [13]),
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<14>_rt_5736 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [14])
  );
  MUXCY   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<14>  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [13]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<14>_rt_5736 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [14])
  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_xor<13>  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [12]),
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<13>_rt_5737 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [13])
  );
  MUXCY   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<13>  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [12]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<13>_rt_5737 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [13])
  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_xor<12>  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [11]),
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<12>_rt_5738 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [12])
  );
  MUXCY   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<12>  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [11]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<12>_rt_5738 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [12])
  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_xor<11>  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [10]),
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<11>_rt_5739 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [11])
  );
  MUXCY   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<11>  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [10]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<11>_rt_5739 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [11])
  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_xor<10>  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [9]),
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<10>_rt_5740 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [10])
  );
  MUXCY   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<10>  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [9]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<10>_rt_5740 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [10])
  );
  XORCY   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_xor<9>  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [8]),
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<9>_rt_5741 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [9])
  );
  MUXCY   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<9>  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [8]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<9>_rt_5741 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [9])
  );
  XORCY   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_xor<8>  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [7]),
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<8>_rt_5742 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [8])
  );
  MUXCY   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<8>  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [7]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<8>_rt_5742 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [8])
  );
  XORCY   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_xor<7>  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [6]),
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<7>_rt_5743 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [7])
  );
  MUXCY   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<7>  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [6]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<7>_rt_5743 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [7])
  );
  XORCY   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_xor<6>  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [5]),
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<6>_rt_5744 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [6])
  );
  MUXCY   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<6>  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [5]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<6>_rt_5744 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [6])
  );
  XORCY   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_xor<5>  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [4]),
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<5>_rt_5745 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<5>1 )
  );
  MUXCY   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<5>  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [4]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<5>_rt_5745 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [5])
  );
  XORCY   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_xor<4>  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [3]),
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<4>_rt_5746 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<4>1 )
  );
  MUXCY   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<4>  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [3]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<4>_rt_5746 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [4])
  );
  XORCY   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_xor<3>  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [2]),
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<3>_rt_5747 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<3>1 )
  );
  MUXCY   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<3>  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [2]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<3>_rt_5747 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [3])
  );
  XORCY   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_xor<2>  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [1]),
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<2>_rt_5748 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<2>1 )
  );
  MUXCY   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<2>  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [1]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<2>_rt_5748 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [2])
  );
  XORCY   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_xor<1>  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [0]),
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<1>_rt_5749 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<1>1 )
  );
  MUXCY   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<1>  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [0]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<1>_rt_5749 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [1])
  );
  XORCY   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_xor<0>  (
    .CI(NlwRenamedSig_OI_drp_dwe),
    .LI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_lut [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<0>1 )
  );
  MUXCY   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<0>  (
    .CI(NlwRenamedSig_OI_drp_dwe),
    .DI(N0),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_lut [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy [0])
  );
  XORCY   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_xor<7>  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy [6]),
    .LI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_xor<7>_rt_5761 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<7>1 )
  );
  XORCY   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_xor<6>  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy [5]),
    .LI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<6>_rt_5750 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<6>1 )
  );
  MUXCY   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<6>  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy [5]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<6>_rt_5750 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy [6])
  );
  XORCY   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_xor<5>  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy [4]),
    .LI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<5>_rt_5751 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<5>2 )
  );
  MUXCY   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<5>  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy [4]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<5>_rt_5751 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy [5])
  );
  XORCY   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_xor<4>  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy [3]),
    .LI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<4>_rt_5752 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<4>2 )
  );
  MUXCY   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<4>  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy [3]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<4>_rt_5752 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy [4])
  );
  XORCY   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_xor<3>  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy [2]),
    .LI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<3>_rt_5753 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<3>2 )
  );
  MUXCY   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<3>  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy [2]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<3>_rt_5753 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy [3])
  );
  XORCY   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_xor<2>  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy [1]),
    .LI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<2>_rt_5754 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<2>2 )
  );
  MUXCY   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<2>  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy [1]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<2>_rt_5754 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy [2])
  );
  XORCY   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_xor<1>  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy [0]),
    .LI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<1>_rt_5755 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<1>2 )
  );
  MUXCY   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<1>  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy [0]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<1>_rt_5755 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy [1])
  );
  XORCY   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_xor<0>  (
    .CI(NlwRenamedSig_OI_drp_dwe),
    .LI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_lut [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<0>2 )
  );
  MUXCY   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<0>  (
    .CI(NlwRenamedSig_OI_drp_dwe),
    .DI(N0),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_lut [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy [0])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_15  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o )
,
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [15]),
    .R
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_395_o )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [15])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_14  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o )
,
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [14]),
    .R
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_395_o )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [14])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_13  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o )
,
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [13]),
    .R
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_395_o )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [13])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_12  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o )
,
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [12]),
    .R
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_395_o )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [12])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_11  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o )
,
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [11]),
    .R
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_395_o )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [11])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_10  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o )
,
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [10]),
    .R
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_395_o )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [10])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_9  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o )
,
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [9]),
    .R
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_395_o )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [9])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_8  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o )
,
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [8]),
    .R
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_395_o )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [8])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_7  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o )
,
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [7]),
    .R
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_395_o )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [7])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_6  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o )
,
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [6]),
    .R
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_395_o )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [6])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_5  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o )
,
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<5>1 ),
    .R
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_395_o )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [5])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_4  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o )
,
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<4>1 ),
    .R
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_395_o )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [4])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_3  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o )
,
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<3>1 ),
    .R
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_395_o )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [3])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_2  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o )
,
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<2>1 ),
    .R
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_395_o )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [2])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_1  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o )
,
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<1>1 ),
    .R
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_395_o )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [1])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_0  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o )
,
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<0>1 ),
    .R
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_395_o )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [0])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count_7  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count_control_core_i_pcs_error_block_count[7]_AND_186_o_2239 )
,
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<7>1 ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_error_block_count_OR_394_o )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [7])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count_6  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count_control_core_i_pcs_error_block_count[7]_AND_186_o_2239 )
,
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<6>1 ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_error_block_count_OR_394_o )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [6])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count_5  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count_control_core_i_pcs_error_block_count[7]_AND_186_o_2239 )
,
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<5>2 ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_error_block_count_OR_394_o )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [5])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count_4  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count_control_core_i_pcs_error_block_count[7]_AND_186_o_2239 )
,
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<4>2 ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_error_block_count_OR_394_o )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [4])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count_3  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count_control_core_i_pcs_error_block_count[7]_AND_186_o_2239 )
,
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<3>2 ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_error_block_count_OR_394_o )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [3])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count_2  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count_control_core_i_pcs_error_block_count[7]_AND_186_o_2239 )
,
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<2>2 ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_error_block_count_OR_394_o )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [2])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count_1  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count_control_core_i_pcs_error_block_count[7]_AND_186_o_2239 )
,
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<1>2 ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_error_block_count_OR_394_o )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [1])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count_0  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count_control_core_i_pcs_error_block_count[7]_AND_186_o_2239 )
,
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result<0>2 ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_error_block_count_OR_394_o )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [0])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count_5  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count_control_core_i_pcs_ber_count[5]_AND_185_o_2240 )
,
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [5]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_error_block_count_OR_394_o )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [5])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count_4  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count_control_core_i_pcs_ber_count[5]_AND_185_o_2240 )
,
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [4]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_error_block_count_OR_394_o )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [4])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count_3  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count_control_core_i_pcs_ber_count[5]_AND_185_o_2240 )
,
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [3]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_error_block_count_OR_394_o )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [3])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count_2  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count_control_core_i_pcs_ber_count[5]_AND_185_o_2240 )
,
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [2]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_error_block_count_OR_394_o )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [2])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count_1  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count_control_core_i_pcs_ber_count[5]_AND_185_o_2240 )
,
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [1]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_error_block_count_OR_394_o )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [1])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count_0  (
    .C(clk156),
    .CE
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count_control_core_i_pcs_ber_count[5]_AND_185_o_2240 )
,
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [0]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_error_block_count_OR_394_o )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [0])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int_5  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Result [5]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Mcount_txsequence_int_val ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [5])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int_3  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Result [3]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Mcount_txsequence_int_val ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [3])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int_2  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Result [2]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Mcount_txsequence_int_val ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [2])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int_4  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Result [4]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Mcount_txsequence_int_val ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [4])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int_1  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Result [1]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Mcount_txsequence_int_val ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [1])
  );
  MUXCY_L   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/emuxcy3  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/emuxcyo [2]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ecomp [3]),
    .LO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/emptyg )
  );
  MUXCY_L   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/emuxcy2  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/emuxcyo [1]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ecomp [2]),
    .LO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/emuxcyo [2])
  );
  MUXCY_L   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/emuxcy1  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/emuxcyo [0]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ecomp [1]),
    .LO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/emuxcyo [1])
  );
  MUXCY_L   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/emuxcy0  (
    .CI(N0),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ecomp [0]),
    .LO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/emuxcyo [0])
  );
  MUXCY_L   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/fmuxcy3  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/fmuxcyo [2]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/fcomp [3]),
    .LO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/fullg )
  );
  MUXCY_L   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/fmuxcy2  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/fmuxcyo [1]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/fcomp [2]),
    .LO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/fmuxcyo [2])
  );
  MUXCY_L   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/fmuxcy1  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/fmuxcyo [0]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/fcomp [1]),
    .LO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/fmuxcyo [1])
  );
  MUXCY_L   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/fmuxcy0  (
    .CI(N0),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/fcomp [0]),
    .LO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/fmuxcyo [0])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr_3  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Result<3>1 ),
    .R(txreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] )
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr_2  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Result<2>1 ),
    .R(txreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] )
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr_0  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Result<0>1 ),
    .R(txreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] )
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr_3  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Result [3]),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] )
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr_2  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Result [2]),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] )
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr_0  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Result [0]),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] )
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rag_writesync_3  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rag_writesync0[3]_GND_15_o_mux_66_OUT<3> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rag_writesync [3])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rag_writesync_2  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rag_writesync0[3]_GND_15_o_mux_66_OUT<2> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rag_writesync [2])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rag_writesync_1  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rag_writesync0[3]_GND_15_o_mux_66_OUT<1> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rag_writesync [1])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rag_writesync_0  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rag_writesync0[3]_GND_15_o_mux_66_OUT<0> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rag_writesync [0])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_lastgray_wrclk_3  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_lastgray_wrclk0 [3]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_lastgray_wrclk [3])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_lastgray_wrclk_2  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_lastgray_wrclk0 [2]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_lastgray_wrclk [2])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_lastgray_wrclk_1  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_lastgray_wrclk0 [1]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_lastgray_wrclk [1])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_lastgray_wrclk_0  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_lastgray_wrclk0 [0]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_lastgray_wrclk [0])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_gray_rdclk_3  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_gray_rdclk0 [3]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_gray_rdclk [3])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_gray_rdclk_2  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_gray_rdclk0 [2]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_gray_rdclk [2])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_gray_rdclk_1  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_gray_rdclk0 [1]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_gray_rdclk [1])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_gray_rdclk_0  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_gray_rdclk0 [0]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_gray_rdclk [0])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_lastgray_wrclk0_3  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_lastgray [3]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_lastgray_wrclk0 [3])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_lastgray_wrclk0_2  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_lastgray [2]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_lastgray_wrclk0 [2])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_lastgray_wrclk0_1  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_lastgray [1]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_lastgray_wrclk0 [1])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_lastgray_wrclk0_0  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_lastgray [0]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_lastgray_wrclk0 [0])
  );
  FDSE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_lastgray_3  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_gray [3]),
    .S(txreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_lastgray [3])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_lastgray_2  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_gray [2]),
    .R(txreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_lastgray [2])
  );
  FDSE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_lastgray_1  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_gray [1]),
    .S(txreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_lastgray [1])
  );
  FDSE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_lastgray_0  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_gray [0]),
    .S(txreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_lastgray [0])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_gray_rdclk0_3  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_gray [3]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_gray_rdclk0 [3])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_gray_rdclk0_2  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_gray [2]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_gray_rdclk0 [2])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_gray_rdclk0_1  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_gray [1]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_gray_rdclk0 [1])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_gray_rdclk0_0  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_gray [0]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_gray_rdclk0 [0])
  );
  FDR #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/full_int  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/fullg ),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/full_int_838 )
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rag_writesync0_3  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_truegray[3]_GND_15_o_mux_65_OUT<3> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rag_writesync0 [3])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rag_writesync0_2  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_truegray[3]_GND_15_o_mux_65_OUT<2> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rag_writesync0 [2])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rag_writesync0_1  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_truegray[3]_GND_15_o_mux_65_OUT<1> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rag_writesync0 [1])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rag_writesync0_0  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_truegray[3]_GND_15_o_mux_65_OUT<0> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rag_writesync0 [0])
  );
  FDSE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_gray_3  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [3]),
    .S(txreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_gray [3])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_gray_2  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [2]),
    .R(txreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_gray [2])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_gray_1  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [1]),
    .R(txreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_gray [1])
  );
  FDSE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_gray_0  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .S(txreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_gray [0])
  );
  FDSE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_gray_3  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [3]),
    .S(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_gray [3])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_gray_2  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [2]),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_gray [2])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_gray_1  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [1]),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_gray [1])
  );
  FDSE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_gray_0  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .S(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_gray [0])
  );
  FDSE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray_3  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .S(txreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [3])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray_2  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3]_rd_addr[2]_XOR_2_o ),
    .R(txreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [2])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray_1  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2]_rd_addr[1]_XOR_3_o ),
    .R(txreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [1])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray_0  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Result<1>1_2327 ),
    .R(txreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_truegray_3  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .R(txreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_truegray [3])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_truegray_2  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3]_rd_addr[2]_XOR_2_o ),
    .R(txreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_truegray [2])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_truegray_1  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2]_rd_addr[1]_XOR_3_o ),
    .R(txreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_truegray [1])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_truegray_0  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Result<1>1_2327 ),
    .R(txreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_truegray [0])
  );
  FDSE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray_3  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .S(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [3])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray_2  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3]_wr_addr[2]_XOR_5_o ),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [2])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray_1  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2]_wr_addr[1]_XOR_6_o ),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [1])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray_0  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Result [1]),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[65].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [65]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[65].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [65])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[64].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [64]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[64].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [64])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[63].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [63]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[63].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [63])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[62].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [62]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[62].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [62])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[61].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [61]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[61].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [61])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[60].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [60]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[60].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [60])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[59].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [59]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[59].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [59])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[58].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [58]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[58].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [58])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[57].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [57]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[57].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [57])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[56].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [56]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[56].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [56])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[55].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [55]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[55].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [55])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[54].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [54]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[54].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [54])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[53].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [53]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[53].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [53])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[52].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [52]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[52].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [52])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[51].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [51]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[51].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [51])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[50].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [50]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[50].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [50])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[49].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [49]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[49].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [49])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[48].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [48]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[48].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [48])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[47].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [47]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[47].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [47])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[46].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [46]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[46].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [46])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[45].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [45]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[45].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [45])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[44].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [44]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[44].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [44])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[43].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [43]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[43].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [43])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[42].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [42]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[42].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [42])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[41].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [41]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[41].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [41])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[40].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [40]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[40].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [40])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[39].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [39]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[39].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [39])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[38].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [38]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[38].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [38])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[37].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [37]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[37].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [37])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[36].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [36]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[36].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [36])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[35].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [35]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[35].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [35])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[34].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [34]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[34].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [34])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[33].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [33]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[33].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [33])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[32].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [32]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[32].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [32])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[31].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [31]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[31].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [31])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[30].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [30]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[30].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [30])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[29].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [29]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[29].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [29])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[28].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [28]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[28].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [28])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[27].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [27]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[27].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [27])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[26].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [26]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[26].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [26])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[25].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [25]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[25].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [25])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[24].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [24]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[24].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [24])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[23].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [23]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[23].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [23])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[22].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [22]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[22].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [22])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[21].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [21]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[21].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [21])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[20].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [20]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[20].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [20])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[19].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [19]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[19].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [19])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[18].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [18]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[18].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [18])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[17].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [17]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[17].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [17])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[16].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [16]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[16].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [16])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[15].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [15]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[15].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [15])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[14].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [14]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[14].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [14])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[13].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [13]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[13].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [13])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[12].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [12]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[12].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [12])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[11].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [11]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[11].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [11])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[10].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [10]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[10].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [10])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[9].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [9]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[9].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [9])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[8].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [8]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[8].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [8])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[7].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [7]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[7].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [7])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[6].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [6]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[6].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [6])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[5].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [5]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[5].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [5])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[4].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [4]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[4].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [4])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[3].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [3]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[3].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [3])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[2].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [2]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[2].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [2])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[1].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [1]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[1].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [1])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[0].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [0]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .WCLK(clk156),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en ),
    .SPO(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[0].ram_i_SPO_UNCONNECTED ),
    .DPO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [0])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[65].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [65]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [65])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[64].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [64]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [64])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[63].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [63]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [63])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[62].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [62]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [62])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[61].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [61]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [61])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[60].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [60]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [60])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[59].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [59]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [59])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[58].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [58]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [58])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[57].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [57]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [57])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[56].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [56]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [56])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[55].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [55]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [55])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[54].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [54]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [54])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[53].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [53]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [53])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[52].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [52]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [52])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[51].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [51]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [51])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[50].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [50]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [50])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[49].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [49]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [49])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[48].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [48]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [48])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[47].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [47]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [47])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[46].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [46]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [46])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[45].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [45]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [45])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[44].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [44]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [44])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[43].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [43]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [43])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[42].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [42]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [42])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[41].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [41]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [41])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[40].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [40]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [40])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[39].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [39]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [39])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[38].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [38]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [38])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[37].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [37]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [37])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[36].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [36]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [36])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[35].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [35]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [35])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[34].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [34]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [34])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[33].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [33]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [33])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[32].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [32]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [32])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[31].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [31]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [31])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[30].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [30]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [30])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[29].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [29]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [29])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[28].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [28]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [28])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[27].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [27]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [27])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[26].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [26]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [26])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[25].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [25]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [25])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[24].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [24]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [24])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[23].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [23]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [23])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[22].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [22]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [22])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[21].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [21]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [21])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[20].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [20]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [20])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[19].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [19]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [19])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[18].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [18]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [18])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[17].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [17]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [17])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[16].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [16]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [16])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[15].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [15]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [15])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[14].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [14]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [14])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[13].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [13]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [13])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[12].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [12]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [12])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[11].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [11]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [11])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[10].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [10]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [10])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[9].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [9]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [9])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[8].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [8]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [8])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[7].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [7]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [7])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[6].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [6]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [6])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[5].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [5]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [5])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[4].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [4]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [4])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[3].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [3]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [3])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[2].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [2]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [2])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[1].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [1]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [1])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/GLOOP[0].fd_i  (
    .C(txusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [0]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [0])
  );
  FDR #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/can_insert_fdr4  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/can_insert_rd_tmp ),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/can_insert_rd )
  );
  FDR #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/can_insert_fdr3  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/can_insert_wra_comb ),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/can_insert_rd_tmp )
  );
  FDR #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/can_insert_fdr2  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/can_insert_wra ),
    .R(rxreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/can_insert_wra2 )
  );
  FDR #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/can_insert_fdr1  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/can_insert ),
    .R(rxreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/can_insert_wra )
  );
  MUXCY_L 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i0/muxcy_i0  (
    .CI(N0),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i0/comp [0]),
    .LO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i0/muxcyo [0])
  );
  MUXCY_L 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i0/muxcy_i1  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i0/muxcyo [0])
,
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i0/comp [1]),
    .LO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i0/muxcyo [1])
  );
  MUXCY_L 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i0/muxcy_i2  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i0/muxcyo [1])
,
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i0/comp [2]),
    .LO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_seq_comb [0])
  );
  MUXCY_L 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i1/muxcy_i0  (
    .CI(N0),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i1/comp [0]),
    .LO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i1/muxcyo [0])
  );
  MUXCY_L 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i1/muxcy_i1  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i1/muxcyo [0])
,
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i1/comp [1]),
    .LO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i1/muxcyo [1])
  );
  MUXCY_L 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i1/muxcy_i2  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i1/muxcyo [1])
,
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i1/comp [2]),
    .LO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_seq_comb [1])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd2  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd2-In ),
    .R(rxreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd2_2878 )
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3-In ),
    .R(rxreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3_2877 )
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1-In ),
    .R(rxreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out_7  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out[7]_GND_34_o_mux_32_OUT<7> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out [7])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out_6  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out[7]_GND_34_o_mux_32_OUT<6> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out [6])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out_5  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out[7]_GND_34_o_mux_32_OUT<5> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out [5])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out_4  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out[7]_GND_34_o_mux_32_OUT<4> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out [4])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out_3  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out[7]_GND_34_o_mux_32_OUT<3> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out [3])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out_2  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out[7]_GND_34_o_mux_32_OUT<2> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out [2])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out_1  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out[7]_GND_34_o_mux_32_OUT<1> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out [1])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out_0  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out[7]_GND_34_o_mux_32_OUT<0> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out [0])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_63  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<63> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [63])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_62  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<62> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [62])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_61  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<61> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [61])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_60  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<60> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [60])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_59  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<59> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [59])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_58  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<58> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [58])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_57  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<57> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [57])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_56  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<56> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [56])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_55  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<55> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [55])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_54  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<54> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [54])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_53  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<53> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [53])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_52  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<52> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [52])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_51  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<51> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [51])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_50  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<50> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [50])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_49  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<49> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [49])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_48  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<48> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [48])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_47  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<47> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [47])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_46  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<46> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [46])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_45  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<45> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [45])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_44  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<44> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [44])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_43  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<43> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [43])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_42  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<42> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [42])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_41  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<41> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [41])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_40  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<40> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [40])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_39  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<39> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [39])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_38  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<38> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [38])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_37  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<37> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [37])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_36  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<36> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [36])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_35  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<35> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [35])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_34  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<34> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [34])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_33  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<33> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [33])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_32  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<32> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [32])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_31  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<31> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [31])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_30  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<30> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [30])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_29  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<29> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [29])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_28  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<28> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [28])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_27  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<27> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [27])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_26  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<26> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [26])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_25  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<25> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [25])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_24  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<24> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [24])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_23  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<23> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [23])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_22  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<22> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [22])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_21  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<21> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [21])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_20  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<20> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [20])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_19  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<19> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [19])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_18  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<18> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [18])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_17  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<17> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [17])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_16  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<16> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [16])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_15  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<15> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [15])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_14  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<14> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [14])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_13  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<13> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [13])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_12  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<12> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [12])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_11  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<11> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [11])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_10  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<10> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [10])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_9  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<9> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [9])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_8  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<8> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [8])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_7  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<7> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [7])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_6  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<6> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [6])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_5  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<5> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [5])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_4  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<4> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [4])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_3  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<3> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [3])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_2  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<2> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [2])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_1  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<1> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [1])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out_0  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<0> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [0])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_delay_7  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_delay[7]_GND_34_o_mux_19_OUT<3> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_delay [7])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_delay_6  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_delay[7]_GND_34_o_mux_19_OUT<2> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_delay [6])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_delay_5  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_delay[7]_GND_34_o_mux_19_OUT<1> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_delay [5])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_delay_4  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_delay[7]_GND_34_o_mux_19_OUT<0> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_delay [4])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay_63  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<31> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [63])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay_62  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<30> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [62])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay_61  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<29> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [61])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay_60  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<28> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [60])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay_59  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<27> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [59])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay_58  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<26> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [58])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay_57  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<25> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [57])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay_56  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<24> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [56])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay_55  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<23> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [55])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay_54  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<22> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [54])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay_53  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<21> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [53])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay_52  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<20> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [52])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay_51  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<19> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [51])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay_50  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<18> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [50])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay_49  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<17> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [49])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay_48  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<16> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [48])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay_47  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<15> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [47])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay_46  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<14> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [46])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay_45  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<13> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [45])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay_44  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<12> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [44])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay_43  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<11> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [43])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay_42  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<10> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [42])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay_41  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<9> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [41])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay_40  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<8> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [40])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay_39  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<7> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [39])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay_38  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<6> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [38])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay_37  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<5> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [37])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay_36  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<4> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [36])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay_35  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<3> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [35])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay_34  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<2> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [34])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay_33  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<1> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [33])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay_32  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<0> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [32])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_was_idle  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_idle [1]),
    .R(rxreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_was_idle_2766 )
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_was_seq  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_seq [1]),
    .R(rxreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_was_seq_2765 )
  );
  FDSE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_seq_1  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_seq_comb [1]),
    .S(rxreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_seq [1])
  );
  FDSE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_seq_0  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_seq_comb [0]),
    .S(rxreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_seq [0])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_idle_1  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_idle_comb [1]),
    .R(rxreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_idle [1])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_idle_0  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_idle_comb [0]),
    .R(rxreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_idle [0])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_63  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<63> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [63])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_62  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<62> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [62])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_61  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<61> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [61])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_60  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<60> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [60])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_59  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<59> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [59])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_58  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<58> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [58])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_57  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<57> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [57])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_56  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<56> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [56])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_55  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<55> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [55])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_54  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<54> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [54])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_53  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<53> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [53])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_52  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<52> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [52])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_51  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<51> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [51])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_50  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<50> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [50])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_49  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<49> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [49])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_48  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<48> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [48])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_47  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<47> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [47])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_46  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<46> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [46])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_45  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<45> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [45])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_44  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<44> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [44])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_43  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<43> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [43])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_42  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<42> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [42])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_41  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<41> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [41])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_40  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<40> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [40])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_39  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<39> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [39])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_38  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<38> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [38])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_37  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<37> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [37])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_36  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<36> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [36])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_35  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<35> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [35])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_34  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<34> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [34])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_33  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<33> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [33])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_32  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<32> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [32])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_31  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<31> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [31])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_30  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<30> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [30])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_29  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<29> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [29])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_28  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<28> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [28])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_27  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<27> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [27])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_26  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<26> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [26])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_25  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<25> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [25])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_24  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<24> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [24])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_23  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<23> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [23])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_22  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<22> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [22])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_21  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<21> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [21])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_20  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<20> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [20])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_19  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<19> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [19])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_18  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<18> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [18])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_17  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<17> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [17])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_16  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<16> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [16])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_15  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<15> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [15])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_14  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<14> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [14])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_13  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<13> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [13])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_12  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<12> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [12])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_11  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<11> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [11])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_10  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<10> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [10])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_9  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<9> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [9])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_8  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<8> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [8])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_7  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<7> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [7])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_6  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<6> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [6])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_5  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<5> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [5])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_4  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<4> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [4])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_3  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<3> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [3])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_2  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<2> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [2])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_1  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<1> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [1])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe_0  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<0> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [0])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe_7  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe[7]_GND_34_o_mux_7_OUT<7> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe [7])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe_6  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe[7]_GND_34_o_mux_7_OUT<6> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe [6])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe_5  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe[7]_GND_34_o_mux_7_OUT<5> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe [5])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe_4  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe[7]_GND_34_o_mux_7_OUT<4> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe [4])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe_3  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe[7]_GND_34_o_mux_7_OUT<3> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe [3])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe_2  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe[7]_GND_34_o_mux_7_OUT<2> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe [2])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe_1  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe[7]_GND_34_o_mux_7_OUT<1> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe [1])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe_0  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe[7]_GND_34_o_mux_7_OUT<0> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe [0])
  );
  MUXCY_L 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/muxcy_i7  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/muxcyo [6]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/comp [7]),
    .LO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/muxcyo [7])
  );
  MUXCY_L 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/muxcy_i5  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/muxcyo [4]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/comp [5]),
    .LO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/muxcyo [5])
  );
  MUXCY_L 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/muxcy_i3  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/muxcyo [2]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/comp [3]),
    .LO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/muxcyo [3])
  );
  MUXCY_L 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/muxcy_i1  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/muxcyo [0]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/comp [1]),
    .LO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/muxcyo [1])
  );
  MUXCY_L 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/muxcy_i8  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/muxcyo [7]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/comp [8]),
    .LO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_idle_comb [1])
  );
  MUXCY_L 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/muxcy_i6  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/muxcyo [5]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/comp [6]),
    .LO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/muxcyo [6])
  );
  MUXCY_L 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/muxcy_i4  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/muxcyo [3]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/comp [4]),
    .LO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/muxcyo [4])
  );
  MUXCY_L 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/muxcy_i2  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/muxcyo [1]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/comp [2]),
    .LO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/muxcyo [2])
  );
  MUXCY_L 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/muxcy_i0  (
    .CI(N0),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/comp [0]),
    .LO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/muxcyo [0])
  );
  MUXCY_L 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/muxcy_i7  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/muxcyo [6]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/comp [7]),
    .LO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/muxcyo [7])
  );
  MUXCY_L 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/muxcy_i5  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/muxcyo [4]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/comp [5]),
    .LO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/muxcyo [5])
  );
  MUXCY_L 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/muxcy_i3  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/muxcyo [2]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/comp [3]),
    .LO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/muxcyo [3])
  );
  MUXCY_L 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/muxcy_i1  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/muxcyo [0]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/comp [1]),
    .LO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/muxcyo [1])
  );
  MUXCY_L 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/muxcy_i8  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/muxcyo [7]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/comp [8]),
    .LO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_idle_comb [0])
  );
  MUXCY_L 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/muxcy_i6  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/muxcyo [5]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/comp [6]),
    .LO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/muxcyo [6])
  );
  MUXCY_L 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/muxcy_i4  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/muxcyo [3]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/comp [4]),
    .LO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/muxcyo [4])
  );
  MUXCY_L 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/muxcy_i2  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/muxcyo [1]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/comp [2]),
    .LO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/muxcyo [2])
  );
  MUXCY_L 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/muxcy_i0  (
    .CI(N0),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/comp [0]),
    .LO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/muxcyo [0])
  );
  MUXCY_L   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/emuxcy3  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/emuxcyo [2]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ecomp [3]),
    .LO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/emptyg )
  );
  MUXCY_L   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/emuxcy2  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/emuxcyo [1]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ecomp [2]),
    .LO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/emuxcyo [2])
  );
  MUXCY_L   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/emuxcy1  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/emuxcyo [0]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ecomp [1]),
    .LO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/emuxcyo [1])
  );
  MUXCY_L   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/emuxcy0  (
    .CI(N0),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ecomp [0]),
    .LO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/emuxcyo [0])
  );
  MUXCY_L   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/fmuxcy3  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/fmuxcyo [2]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/fcomp [3]),
    .LO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/fullg )
  );
  MUXCY_L   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/fmuxcy2  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/fmuxcyo [1]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/fcomp [2]),
    .LO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/fmuxcyo [2])
  );
  MUXCY_L   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/fmuxcy1  (
    .CI(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/fmuxcyo [0]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/fcomp [1]),
    .LO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/fmuxcyo [1])
  );
  MUXCY_L   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/fmuxcy0  (
    .CI(N0),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/fcomp [0]),
    .LO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/fmuxcyo [0])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr_3  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Result<3>1 ),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr_2  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Result<2>1 ),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr_1  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Result<1>1_2989 ),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr_0  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Result<0>1 ),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_3  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Result [3]),
    .R(rxreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_2  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Result [2]),
    .R(rxreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_1  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Result [1]),
    .R(rxreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_0  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Result [0]),
    .R(rxreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/status_3  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/full_int_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe[3]_ra_writesync[3]_sub_81_OUT<3> )
,
    .R(rxreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/status [3])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/status_2  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/full_int_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe[3]_ra_writesync[3]_sub_81_OUT<2> )
,
    .R(rxreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/status [2])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray_wrclk_3  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray_wrclk0 [3]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray_wrclk [3])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray_wrclk_2  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray_wrclk0 [2]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray_wrclk [2])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray_wrclk_1  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray_wrclk0 [1]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray_wrclk [1])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray_wrclk_0  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray_wrclk0 [0]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray_wrclk [0])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray_wrclk0_3  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray [3]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray_wrclk0 [3])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray_wrclk0_2  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray [2]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray_wrclk0 [2])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray_wrclk0_1  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray [1]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray_wrclk0 [1])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray_wrclk0_0  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray [0]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray_wrclk0 [0])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray_3  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/_n0201_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray[3]_PWR_39_o_mux_31_OUT<3> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray [3])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray_2  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/_n0201_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray[3]_PWR_39_o_mux_31_OUT<2> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray [2])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray_1  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/_n0201_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray[3]_PWR_39_o_mux_31_OUT<1> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray [1])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray_0  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/_n0201_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray[3]_PWR_39_o_mux_31_OUT<0> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray [0])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray_rdclk_3  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray_rdclk0 [3]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray_rdclk [3])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray_rdclk_2  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray_rdclk0 [2]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray_rdclk [2])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray_rdclk_1  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray_rdclk0 [1]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray_rdclk [1])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray_rdclk_0  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray_rdclk0 [0]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray_rdclk [0])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray_rdclk0_3  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray [3]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray_rdclk0 [3])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray_rdclk0_2  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray [2]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray_rdclk0 [2])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray_rdclk0_1  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray [1]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray_rdclk0 [1])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray_rdclk0_0  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray [0]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray_rdclk0 [0])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync_3  (
    .C(rxusrclk2),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync0[3]_GND_37_o_mux_66_OUT<3> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync [3])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync_2  (
    .C(rxusrclk2),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync0[3]_GND_37_o_mux_66_OUT<2> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync [2])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync_1  (
    .C(rxusrclk2),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync0[3]_GND_37_o_mux_66_OUT<1> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync [1])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync_0  (
    .C(rxusrclk2),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync0[3]_GND_37_o_mux_66_OUT<0> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync [0])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_gray_3  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/_n0201_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_gray[3]_PWR_39_o_mux_25_OUT<3> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_gray [3])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_gray_2  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/_n0201_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_gray[3]_PWR_39_o_mux_25_OUT<2> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_gray [2])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_gray_1  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/_n0201_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_gray[3]_PWR_39_o_mux_25_OUT<1> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_gray [1])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_gray_0  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/_n0201_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_gray[3]_PWR_39_o_mux_25_OUT<0> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_gray [0])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray_3  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/_n0210_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray[3]_PWR_39_o_mux_50_OUT<3> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray [3])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray_2  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/_n0210_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray[3]_PWR_39_o_mux_50_OUT<2> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray [2])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray_1  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/_n0210_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray[3]_PWR_39_o_mux_50_OUT<1> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray [1])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray_0  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/_n0210_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray[3]_PWR_39_o_mux_50_OUT<0> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray [0])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync0_3  (
    .C(rxusrclk2),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_truegray[3]_GND_37_o_mux_65_OUT<3> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync0 [3])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync0_2  (
    .C(rxusrclk2),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_truegray[3]_GND_37_o_mux_65_OUT<2> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync0 [2])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync0_1  (
    .C(rxusrclk2),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_truegray[3]_GND_37_o_mux_65_OUT<1> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync0 [1])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync0_0  (
    .C(rxusrclk2),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_truegray[3]_GND_37_o_mux_65_OUT<0> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync0 [0])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_nextgray_3  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/_n0201_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_nextgray[3]_PWR_39_o_mux_19_OUT<3> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_nextgray [3])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_nextgray_2  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/_n0201_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_nextgray[3]_PWR_39_o_mux_19_OUT<2> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_nextgray [2])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_nextgray_1  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/_n0201_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_nextgray[3]_PWR_39_o_mux_19_OUT<1> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_nextgray [1])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_nextgray_3  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/_n0210_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_nextgray[3]_PWR_39_o_mux_44_OUT<3> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_nextgray [3])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_nextgray_2  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/_n0210_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_nextgray[3]_PWR_39_o_mux_44_OUT<2> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_nextgray [2])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_nextgray_1  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/_n0210_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_nextgray[3]_PWR_39_o_mux_44_OUT<1> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_nextgray [1])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe_3  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe1 [3]),
    .R(rxreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe [3])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe_2  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe1 [2]),
    .R(rxreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe [2])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe_1  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe1 [1]),
    .R(rxreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe [1])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe_0  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe1 [0]),
    .R(rxreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe [0])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_truegray_3  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_truegray [3])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_truegray_2  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr[3]_rd_addr[2]_XOR_509_o )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_truegray [2])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_truegray_1  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr[2]_rd_addr[1]_XOR_510_o )
,
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_truegray [1])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_truegray_0  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Result<1>1_2989 ),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_truegray [0])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe1_3  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe0 [3]),
    .R(rxreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe1 [3])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe1_2  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe0 [2]),
    .R(rxreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe1 [2])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe1_1  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe0 [1]),
    .R(rxreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe1 [1])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe1_0  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe0 [0]),
    .R(rxreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe1 [0])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe0_3  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .R(rxreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe0 [3])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe0_2  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .R(rxreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe0 [2])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe0_1  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .R(rxreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe0 [1])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe0_0  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .R(rxreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe0 [0])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[71].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out [7]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[71].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [71])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[70].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out [6]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[70].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [70])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[69].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out [5]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[69].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [69])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[68].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out [4]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[68].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [68])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[67].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out [3]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[67].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [67])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[66].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out [2]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[66].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [66])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[65].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out [1]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[65].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [65])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[64].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out [0]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[64].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [64])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[63].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [63]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[63].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [63])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[62].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [62]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[62].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [62])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[61].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [61]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[61].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [61])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[60].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [60]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[60].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [60])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[59].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [59]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[59].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [59])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[58].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [58]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[58].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [58])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[57].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [57]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[57].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [57])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[56].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [56]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[56].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [56])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[55].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [55]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[55].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [55])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[54].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [54]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[54].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [54])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[53].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [53]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[53].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [53])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[52].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [52]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[52].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [52])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[51].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [51]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[51].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [51])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[50].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [50]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[50].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [50])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[49].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [49]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[49].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [49])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[48].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [48]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[48].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [48])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[47].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [47]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[47].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [47])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[46].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [46]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[46].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [46])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[45].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [45]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[45].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [45])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[44].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [44]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[44].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [44])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[43].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [43]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[43].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [43])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[42].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [42]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[42].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [42])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[41].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [41]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[41].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [41])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[40].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [40]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[40].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [40])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[39].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [39]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[39].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [39])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[38].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [38]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[38].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [38])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[37].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [37]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[37].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [37])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[36].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [36]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[36].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [36])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[35].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [35]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[35].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [35])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[34].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [34]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[34].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [34])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[33].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [33]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[33].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [33])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[32].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [32]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[32].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [32])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[31].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [31]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[31].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [31])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[30].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [30]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[30].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [30])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[29].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [29]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[29].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [29])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[28].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [28]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[28].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [28])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[27].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [27]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[27].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [27])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[26].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [26]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[26].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [26])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[25].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [25]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[25].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [25])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[24].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [24]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[24].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [24])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[23].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [23]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[23].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [23])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[22].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [22]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[22].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [22])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[21].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [21]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[21].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [21])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[20].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [20]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[20].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [20])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[19].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [19]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[19].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [19])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[18].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [18]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[18].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [18])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[17].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [17]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[17].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [17])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[16].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [16]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[16].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [16])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[15].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [15]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[15].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [15])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[14].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [14]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[14].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [14])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[13].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [13]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[13].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [13])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[12].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [12]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[12].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [12])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[11].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [11]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[11].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [11])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[10].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [10]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[10].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [10])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[9].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [9]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[9].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [9])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[8].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [8]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[8].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [8])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[7].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [7]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[7].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [7])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[6].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [6]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[6].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [6])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[5].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [5]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[5].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [5])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[4].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [4]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[4].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [4])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[3].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [3]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[3].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [3])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[2].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [2]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[2].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [2])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[1].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [1]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[1].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [1])
  );
  RAM16X1D #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[0].ram_i  (
    .A0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .A1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .A2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .A3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out [0]),
    .DPRA0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .DPRA1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .DPRA2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .DPRA3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .WCLK(rxusrclk2),
    .WE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en ),
    .SPO
(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[0].ram_i_SPO_UNCONNECTED )
,
    .DPO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [0])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[71].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [71]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [71])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[70].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [70]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [70])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[69].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [69]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [69])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[68].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [68]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [68])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[67].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [67]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [67])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[66].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [66]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [66])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[65].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [65]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [65])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[64].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [64]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [64])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[63].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [63]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [63])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[62].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [62]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [62])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[61].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [61]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [61])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[60].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [60]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [60])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[59].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [59]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [59])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[58].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [58]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [58])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[57].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [57]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [57])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[56].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [56]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [56])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[55].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [55]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [55])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[54].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [54]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [54])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[53].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [53]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [53])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[52].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [52]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [52])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[51].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [51]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [51])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[50].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [50]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [50])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[49].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [49]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [49])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[48].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [48]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [48])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[47].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [47]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [47])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[46].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [46]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [46])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[45].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [45]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [45])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[44].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [44]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [44])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[43].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [43]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [43])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[42].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [42]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [42])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[41].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [41]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [41])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[40].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [40]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [40])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[39].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [39]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [39])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[38].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [38]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [38])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[37].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [37]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [37])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[36].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [36]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [36])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[35].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [35]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [35])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[34].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [34]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [34])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[33].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [33]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [33])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[32].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [32]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [32])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[31].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [31]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [31])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[30].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [30]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [30])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[29].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [29]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [29])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[28].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [28]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [28])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[27].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [27]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [27])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[26].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [26]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [26])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[25].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [25]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [25])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[24].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [24]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [24])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[23].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [23]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [23])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[22].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [22]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [22])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[21].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [21]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [21])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[20].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [20]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [20])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[19].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [19]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [19])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[18].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [18]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [18])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[17].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [17]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [17])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[16].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [16]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [16])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[15].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [15]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [15])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[14].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [14]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [14])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[13].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [13]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [13])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[12].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [12]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [12])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[11].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [11]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [11])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[10].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [10]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [10])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[9].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [9]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [9])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[8].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [8]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [8])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[7].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [7]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [7])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[6].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [6]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [6])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[5].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [5]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [5])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[4].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [4]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [4])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[3].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [3]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [3])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[2].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [2]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [2])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[1].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [1]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [1])
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/GLOOP[0].fd_i  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/rd_data_unreg [0]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [0])
  );
  MUXCY_L 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/muxcy_i0  (
    .CI(N0),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/comp [0]),
    .LO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/muxcyo [0])
  );
  MUXCY_L 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/muxcy_i2  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/muxcyo [1]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/comp [2]),
    .LO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/muxcyo [2])
  );
  MUXCY_L 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/muxcy_i4  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/muxcyo [3]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/comp [4]),
    .LO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/muxcyo [4])
  );
  MUXCY_L 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/muxcy_i6  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/muxcyo [5]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/comp [6]),
    .LO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/muxcyo [6])
  );
  MUXCY_L 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/muxcy_i8  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/muxcyo [7]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/comp [8]),
    .LO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/is_idle [1])
  );
  MUXCY_L 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/muxcy_i1  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/muxcyo [0]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/comp [1]),
    .LO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/muxcyo [1])
  );
  MUXCY_L 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/muxcy_i3  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/muxcyo [2]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/comp [3]),
    .LO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/muxcyo [3])
  );
  MUXCY_L 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/muxcy_i5  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/muxcyo [4]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/comp [5]),
    .LO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/muxcyo [5])
  );
  MUXCY_L 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/muxcy_i7  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/muxcyo [6]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/comp [7]),
    .LO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/muxcyo [7])
  );
  MUXCY_L 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/muxcy_i0  (
    .CI(N0),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/comp [0]),
    .LO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/muxcyo [0])
  );
  MUXCY_L 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/muxcy_i2  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/muxcyo [1]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/comp [2]),
    .LO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/muxcyo [2])
  );
  MUXCY_L 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/muxcy_i4  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/muxcyo [3]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/comp [4]),
    .LO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/muxcyo [4])
  );
  MUXCY_L 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/muxcy_i6  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/muxcyo [5]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/comp [6]),
    .LO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/muxcyo [6])
  );
  MUXCY_L 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/muxcy_i8  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/muxcyo [7]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/comp [8]),
    .LO(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/is_idle [0])
  );
  MUXCY_L 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/muxcy_i1  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/muxcyo [0]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/comp [1]),
    .LO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/muxcyo [1])
  );
  MUXCY_L 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/muxcy_i3  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/muxcyo [2]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/comp [3]),
    .LO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/muxcyo [3])
  );
  MUXCY_L 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/muxcy_i5  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/muxcyo [4]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/comp [5]),
    .LO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/muxcyo [5])
  );
  MUXCY_L 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/muxcy_i7  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/muxcyo [6]),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/comp [7]),
    .LO
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/muxcyo [7])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd3  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd3-In ),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd3_3332 )
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/ctrl_out_7  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_in[7]_GND_39_o_mux_22_OUT<7> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/ctrl_out [7])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/ctrl_out_6  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_in[7]_GND_39_o_mux_22_OUT<6> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/ctrl_out [6])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/ctrl_out_5  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_in[7]_GND_39_o_mux_22_OUT<5> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/ctrl_out [5])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/ctrl_out_4  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_in[7]_GND_39_o_mux_22_OUT<4> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/ctrl_out [4])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/ctrl_out_3  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_in[7]_GND_39_o_mux_22_OUT<3> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/ctrl_out [3])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/ctrl_out_2  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_in[7]_GND_39_o_mux_22_OUT<2> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/ctrl_out [2])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/ctrl_out_1  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_in[7]_GND_39_o_mux_22_OUT<1> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/ctrl_out [1])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/ctrl_out_0  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_in[7]_GND_39_o_mux_22_OUT<0> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/ctrl_out [0])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_63  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<63> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [63])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_62  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<62> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [62])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_61  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<61> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [61])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_60  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<60> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [60])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_59  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<59> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [59])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_58  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<58> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [58])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_57  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<57> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [57])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_56  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<56> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [56])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_55  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<55> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [55])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_54  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<54> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [54])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_53  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<53> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [53])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_52  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<52> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [52])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_51  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<51> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [51])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_50  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<50> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [50])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_49  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<49> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [49])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_48  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<48> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [48])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_47  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<47> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [47])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_46  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<46> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [46])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_45  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<45> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [45])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_44  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<44> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [44])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_43  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<43> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [43])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_42  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<42> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [42])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_41  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<41> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [41])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_40  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<40> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [40])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_39  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<39> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [39])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_38  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<38> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [38])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_37  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<37> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [37])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_36  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<36> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [36])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_35  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<35> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [35])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_34  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<34> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [34])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_33  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<33> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [33])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_32  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<32> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [32])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_31  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<31> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [31])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_30  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<30> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [30])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_29  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<29> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [29])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_28  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<28> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [28])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_27  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<27> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [27])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_26  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<26> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [26])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_25  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<25> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [25])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_24  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<24> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [24])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_23  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<23> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [23])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_22  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<22> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [22])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_21  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<21> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [21])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_20  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<20> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [20])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_19  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<19> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [19])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_18  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<18> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [18])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_17  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<17> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [17])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_16  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<16> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [16])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_15  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<15> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [15])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_14  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<14> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [14])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_13  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<13> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [13])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_12  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<12> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [12])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_11  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<11> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [11])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_10  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<10> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [10])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_9  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<9> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [9])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_8  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<8> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [8])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_7  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<7> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [7])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_6  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<6> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [6])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_5  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<5> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [5])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_4  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<4> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [4])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_3  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<3> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [3])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_2  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<2> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [2])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_1  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<1> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [1])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out_0  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<0> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [0])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay_63  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<31> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [63])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay_62  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<30> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [62])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay_61  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<29> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [61])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay_60  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<28> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [60])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay_59  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<27> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [59])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay_58  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<26> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [58])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay_57  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<25> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [57])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay_56  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<24> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [56])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay_55  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<23> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [55])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay_54  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<22> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [54])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay_53  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<21> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [53])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay_52  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<20> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [52])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay_51  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<19> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [51])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay_50  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<18> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [50])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay_49  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<17> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [49])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay_48  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<16> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [48])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay_47  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<15> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [47])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay_46  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<14> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [46])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay_45  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<13> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [45])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay_44  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<12> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [44])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay_43  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<11> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [43])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay_42  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<10> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [42])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay_41  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<9> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [41])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay_40  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<8> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [40])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay_39  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<7> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [39])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay_38  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<6> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [38])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay_37  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<5> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [37])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay_36  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<4> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [36])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay_35  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<3> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [35])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay_34  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<2> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [34])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay_33  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<1> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [33])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay_32  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<0> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [32])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_delay_7  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_in[7]_GND_39_o_mux_3_OUT<3> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_delay [7])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_delay_6  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_in[7]_GND_39_o_mux_3_OUT<2> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_delay [6])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_delay_5  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_in[7]_GND_39_o_mux_3_OUT<1> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_delay [5])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_delay_4  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_in[7]_GND_39_o_mux_3_OUT<0> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_delay [4])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/eq_rxusrclk2_en156  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o_norst ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_inv ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/eq_rxusrclk2_en156_3376 )
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxusrclk2_en156_dup2  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o_norst ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_inv ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxusrclk2_en156_dup2_3377 )
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxusrclk2_en156  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o_norst ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_inv ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 )
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxusrclk2_en156_dup1  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o_norst ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_inv ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxusrclk2_en156_dup1_3378 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_33  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [33]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_33_732 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_34  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [2]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_34_733 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_35  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [3]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_35_734 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_36  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [4]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_36_735 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_37  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [5]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_37_736 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_38  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [6]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_38_737 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_39  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [7]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_39_738 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_40  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [8]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_40_739 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_41  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [9]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_41_740 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_42  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [10]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_42_741 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_44  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [12]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_44_743 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_45  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [13]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_45_744 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_43  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [11]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_43_742 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_46  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [14]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_46_745 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_47  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [15]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_47_746 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_48  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [16]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_48_747 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_49  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [17]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_49_748 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_50  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [18]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_50_749 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_51  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [19]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_51_750 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_53  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [21]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_53_752 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_54  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [22]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_54_753 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_52  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [20]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_52_751 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_55  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [23]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_55_754 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_56  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [24]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_56_755 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_57  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [25]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_57_756 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_58  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [26]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_58_757 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_59  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [27]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_59_758 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_60  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [28]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_60_759 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_62  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [30]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_62_761 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_63  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [31]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_63_762 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_61  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [29]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_61_760 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_64  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [32]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_64_763 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_65  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [33]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_65_764 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_0  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [0]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_0_699 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_1  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [1]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_1_700 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_2  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [2]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_2_701 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_3  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [3]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_3_702 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_4  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [4]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_4_703 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_5  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [5]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_5_704 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_6  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [6]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_6_705 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_7  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [7]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_7_706 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_8  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [8]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_8_707 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_9  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [9]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_9_708 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_10  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [10]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_10_709 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_11  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [11]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_11_710 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_13  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [13]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_13_712 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_14  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [14]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_14_713 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_12  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [12]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_12_711 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_15  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [15]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_15_714 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_16  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [16]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_16_715 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_17  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [17]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_17_716 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_18  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [18]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_18_717 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_19  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [19]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_19_718 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_20  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [20]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_20_719 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_22  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [22]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_22_721 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_23  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [23]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_23_722 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_21  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [21]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_21_720 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_24  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [24]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_24_723 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_25  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [25]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_25_724 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_26  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [26]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_26_725 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_27  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [27]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_27_726 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_28  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [28]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_28_727 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_29  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [29]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_29_728 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_31  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [31]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_31_730 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_32  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [32]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_32_731 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_30  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_34_gt [30]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rx_66_out_30_729 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/d1  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_1_3392 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/d1_3379 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/newedge_reg  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/newedge_3380 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/newedge_reg_3381 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/q  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/out_comb ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/q_3398 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/d1  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_2_3394 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/d1_3383 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/newedge_reg  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/newedge_3384 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/newedge_reg_3385 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/q  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/out_comb ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/q_3397 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/d1  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_3_3393 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/d1_3387 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/newedge_reg  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/newedge_3388 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/newedge_reg_3389 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/q  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/out_comb ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/q_3396 )
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_out  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_sync_1_counter_sync_extra_OR_558_o ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_out_694 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/d1  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_1_3412 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/d1_3399 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/newedge_reg  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/newedge_3400 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/newedge_reg_3401 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/q  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/out_comb ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/q_3418 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/d1  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_2_3414 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/d1_3403 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/newedge_reg  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/newedge_3404 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/newedge_reg_3405 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/q  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/out_comb ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/q_3417 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/d1  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_3_3413 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/d1_3407 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/newedge_reg  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/newedge_3408 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/newedge_reg_3409 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/q  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/out_comb ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/q_3416 )
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_out  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_sync_1_counter_sync_extra_OR_558_o ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_out_695 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/d1  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_1_3432 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/d1_3419 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/newedge_reg  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/newedge_3420 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/newedge_reg_3421 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/q  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/out_comb ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/q_3438 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/d1  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_2_3434 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/d1_3423 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/newedge_reg  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/newedge_3424 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/newedge_reg_3425 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/q  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/out_comb ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/q_3437 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/d1  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_3_3433 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/d1_3427 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/newedge_reg  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/newedge_3428 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/newedge_reg_3429 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/q  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/out_comb ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/q_3436 )
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_out  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_sync_1_counter_sync_extra_OR_558_o ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_out_696 )
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_2  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg[2]_GND_22_o_mux_458_OUT<2> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_1  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg[2]_GND_22_o_mux_458_OUT<1> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [1])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_0  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg[2]_GND_22_o_mux_458_OUT<0> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [0])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg_2  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/PWR_23_o_GND_22_o_mux_218_OUT [2]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n0854 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [2])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg_1  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/PWR_23_o_GND_22_o_mux_218_OUT [1]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n0854 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [1])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg_0  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/PWR_23_o_GND_22_o_mux_218_OUT [0]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n0854 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [0])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c4_6  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n1230_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_347_OUT [6]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c4 [6])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c4_5  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n1230_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_347_OUT [5]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c4 [5])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c4_4  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n1230_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_347_OUT [4]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c4 [4])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c4_3  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n1230_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_347_OUT [3]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c4 [3])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c4_2  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n1230_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_347_OUT [2]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c4 [2])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c4_1  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n1230_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_347_OUT [1]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c4 [1])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c4_0  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n1230_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_347_OUT [0]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c4 [0])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c0_6  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n1043_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_251_OUT [6]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c0 [6])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c0_5  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n1043_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_251_OUT [5]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c0 [5])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c0_4  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n1043_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_251_OUT [4]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c0 [4])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c0_3  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n1043_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_251_OUT [3]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c0 [3])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c0_2  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n1043_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_251_OUT [2]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c0 [2])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c0_1  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n1043_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_251_OUT [1]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c0 [1])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c0_0  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n1043_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_251_OUT [0]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c0 [0])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d7_7  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<7>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [63]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d7 [7])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d7_6  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<7>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [62]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d7 [6])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d7_5  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<7>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [61]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d7 [5])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d7_4  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<7>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [60]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d7 [4])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d7_3  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<7>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [59]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d7 [3])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d7_2  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<7>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [58]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d7 [2])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d7_1  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<7>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [57]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d7 [1])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d7_0  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<7>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [56]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d7 [0])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c7_6  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [7]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT [6]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c7 [6])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c7_5  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [7]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT [5]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c7 [5])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c7_4  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [7]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT [4]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c7 [4])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c7_3  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [7]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT [3]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c7 [3])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c7_2  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [7]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT [2]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c7 [2])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c7_1  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [7]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT [1]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c7 [1])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c7_0  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [7]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT [0]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c7 [0])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d6_7  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<6>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [55]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d6 [7])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d6_6  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<6>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [54]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d6 [6])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d6_5  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<6>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [53]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d6 [5])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d6_4  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<6>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [52]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d6 [4])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d6_3  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<6>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [51]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d6 [3])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d6_2  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<6>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [50]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d6 [2])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d6_1  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<6>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [49]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d6 [1])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d6_0  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<6>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [48]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d6 [0])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d5_7  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<5>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [47]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d5 [7])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d5_6  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<5>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [46]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d5 [6])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d5_5  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<5>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [45]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d5 [5])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d5_4  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<5>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [44]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d5 [4])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d5_3  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<5>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [43]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d5 [3])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d5_2  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<5>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [42]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d5 [2])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d5_1  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<5>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [41]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d5 [1])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d5_0  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<5>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [40]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d5 [0])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c5_6  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [5]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT [6]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c5 [6])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c5_5  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [5]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT [5]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c5 [5])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c5_4  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [5]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT [4]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c5 [4])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c5_3  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [5]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT [3]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c5 [3])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c5_2  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [5]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT [2]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c5 [2])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c5_1  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [5]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT [1]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c5 [1])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c5_0  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [5]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT [0]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c5 [0])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c6_6  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [6]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT [6]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c6 [6])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c6_5  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [6]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT [5]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c6 [5])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c6_4  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [6]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT [4]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c6 [4])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c6_3  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [6]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT [3]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c6 [3])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c6_2  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [6]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT [2]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c6 [2])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c6_1  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [6]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT [1]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c6 [1])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c6_0  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [6]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT [0]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c6 [0])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d4_7  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<4>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [39]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d4 [7])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d4_6  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<4>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [38]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d4 [6])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d4_5  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<4>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [37]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d4 [5])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d4_4  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<4>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [36]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d4 [4])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d4_3  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<4>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [35]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d4 [3])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d4_2  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<4>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [34]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d4 [2])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d4_1  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<4>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [33]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d4 [1])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d4_0  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<4>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [32]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d4 [0])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d3_7  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<3>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [31]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d3 [7])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d3_6  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<3>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [30]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d3 [6])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d3_5  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<3>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [29]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d3 [5])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d3_4  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<3>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [28]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d3 [4])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d3_3  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<3>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [27]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d3 [3])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d3_2  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<3>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [26]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d3 [2])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d3_1  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<3>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [25]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d3 [1])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d3_0  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<3>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [24]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d3 [0])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c3_6  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT [6]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c3 [6])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c3_5  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT [5]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c3 [5])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c3_4  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT [4]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c3 [4])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c3_3  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT [3]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c3 [3])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c3_2  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT [2]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c3 [2])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c3_1  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT [1]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c3 [1])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c3_0  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT [0]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c3 [0])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d2_7  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<2>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [23]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d2 [7])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d2_6  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<2>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [22]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d2 [6])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d2_5  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<2>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [21]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d2 [5])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d2_4  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<2>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [20]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d2 [4])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d2_3  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<2>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [19]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d2 [3])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d2_2  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<2>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [18]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d2 [2])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d2_1  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<2>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [17]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d2 [1])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d2_0  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<2>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [16]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d2 [0])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c2_6  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [2]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT [6]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c2 [6])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c2_5  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [2]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT [5]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c2 [5])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c2_4  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [2]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT [4]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c2 [4])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c2_3  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [2]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT [3]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c2 [3])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c2_2  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [2]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT [2]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c2 [2])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c2_1  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [2]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT [1]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c2 [1])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c2_0  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [2]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT [0]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c2 [0])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c1_6  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [1]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT [6]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c1 [6])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c1_5  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [1]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT [5]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c1 [5])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c1_4  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [1]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT [4]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c1 [4])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c1_3  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [1]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT [3]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c1 [3])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c1_2  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [1]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT [2]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c1 [2])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c1_1  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [1]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT [1]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c1 [1])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c1_0  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [1]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT [0]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c1 [0])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d0_7  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<0>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [7]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d0 [7])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d0_6  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<0>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [6]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d0 [6])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d0_5  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<0>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [5]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d0 [5])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d0_4  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<0>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [4]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d0 [4])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d0_3  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<0>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [3]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d0 [3])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d0_2  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<0>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [2]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d0 [2])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d0_1  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<0>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [1]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d0 [1])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d0_0  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<0>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [0]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d0 [0])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d1_7  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<1>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [15]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d1 [7])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d1_6  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<1>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [14]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d1 [6])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d1_5  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<1>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [13]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d1 [5])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d1_4  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<1>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [12]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d1 [4])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d1_3  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<1>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [11]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d1 [3])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d1_2  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<1>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [10]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d1 [2])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d1_1  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<1>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [9]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d1 [1])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d1_0  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<1>_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [8]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d1 [0])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg_7  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [7]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [7])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg_6  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [6]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [6])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg_5  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [5]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [5])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg_4  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [4]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [4])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg_3  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [3]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [3])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg_2  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [2]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [2])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg_1  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [1]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [1])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg_0  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [0]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [0])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_65  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<65> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [65])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_64  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<64> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [64])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_63  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<63> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [63])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_62  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<62> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [62])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_61  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<61> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [61])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_60  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<60> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [60])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_59  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<59> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [59])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_58  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<58> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [58])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_57  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<57> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [57])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_56  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<56> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [56])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_55  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<55> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [55])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_54  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<54> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [54])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_53  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<53> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [53])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_52  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<52> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [52])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_51  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<51> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [51])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_50  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<50> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [50])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_49  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<49> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [49])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_48  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<48> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [48])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_47  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<47> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [47])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_46  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<46> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [46])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_45  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<45> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [45])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_44  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<44> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [44])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_43  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<43> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [43])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_42  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<42> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [42])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_41  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<41> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [41])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_40  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<40> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [40])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_39  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<39> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [39])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_38  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<38> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [38])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_37  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<37> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [37])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_36  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<36> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [36])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_35  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<35> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [35])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_34  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<34> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [34])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_33  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<33> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [33])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_32  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<32> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [32])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_31  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<31> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [31])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_30  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<30> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [30])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_29  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<29> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [29])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_28  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<28> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [28])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_27  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<27> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [27])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_26  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<26> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [26])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_25  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<25> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [25])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_24  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<24> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [24])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_23  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<23> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [23])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_22  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<22> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [22])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_21  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<21> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [21])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_20  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<20> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [20])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_19  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<19> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [19])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_18  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<18> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [18])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_17  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<17> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [17])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_16  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<16> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [16])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_15  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<15> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [15])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_14  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<14> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [14])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_13  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<13> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [13])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_12  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<12> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [12])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_11  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<11> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [11])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_10  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<10> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [10])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_9  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<9> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [9])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_8  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<8> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [8])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_7  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<7> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [7])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_6  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<6> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [6])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_5  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<5> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [5])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_4  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<4> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [4])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_3  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<3> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [3])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_2  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<2> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [2])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_1  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<1> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [1])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data_0  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<0> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [0])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_7  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg [7]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [7])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_6  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg [6]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [6])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_5  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg [5]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [5])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_4  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg [4]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [4])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_3  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg [3]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [3])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_2  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg [2]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [2])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_1  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg [1]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [1])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_0  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg [0]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [0])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_63  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [63]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [63])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_62  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [62]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [62])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_61  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [61]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [61])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_60  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [60]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [60])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_59  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [59]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [59])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_58  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [58]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [58])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_57  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [57]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [57])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_56  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [56]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [56])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_55  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [55]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [55])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_54  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [54]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [54])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_53  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [53]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [53])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_52  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [52]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [52])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_51  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [51]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [51])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_50  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [50]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [50])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_49  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [49]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [49])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_48  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [48]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [48])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_47  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [47]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [47])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_46  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [46]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [46])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_45  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [45]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [45])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_44  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [44]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [44])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_43  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [43]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [43])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_42  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [42]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [42])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_41  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [41]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [41])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_40  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [40]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [40])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_39  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [39]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [39])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_38  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [38]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [38])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_37  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [37]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [37])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_36  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [36]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [36])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_35  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [35]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [35])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_34  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [34]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [34])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_33  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [33]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [33])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_32  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [32]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [32])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_31  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [31]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [31])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_30  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [30]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [30])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_29  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [29]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [29])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_28  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [28]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [28])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_27  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [27]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [27])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_26  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [26]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [26])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_25  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [25]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [25])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_24  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [24]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [24])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_23  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [23]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [23])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_22  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [22]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [22])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_21  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [21]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [21])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_20  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [20]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [20])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_19  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [19]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [19])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_18  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [18]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [18])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_17  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [17]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [17])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_16  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [16]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [16])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_15  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [15]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [15])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_14  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [14]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [14])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_13  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [13]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [13])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_12  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [12]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [12])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_11  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [11]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [11])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_10  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [10]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [10])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_9  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [9]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [9])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_8  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [8]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [8])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_7  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [7]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [7])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_6  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [6]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [6])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_5  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [5]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [5])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_4  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [4]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [4])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_3  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [3]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [3])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_2  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [2]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [2])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_1  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [1]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [1])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1_0  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [0]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [0])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_63  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [63]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [63])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_62  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [62]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [62])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_61  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [61]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [61])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_60  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [60]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [60])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_59  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [59]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [59])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_58  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [58]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [58])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_57  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [57]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [57])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_56  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [56]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [56])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_55  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [55]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [55])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_54  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [54]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [54])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_53  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [53]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [53])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_52  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [52]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [52])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_51  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [51]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [51])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_50  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [50]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [50])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_49  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [49]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [49])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_48  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [48]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [48])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_47  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [47]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [47])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_46  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [46]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [46])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_45  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [45]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [45])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_44  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [44]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [44])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_43  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [43]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [43])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_42  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [42]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [42])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_41  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [41]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [41])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_40  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [40]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [40])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_39  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [39]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [39])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_38  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [38]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [38])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_37  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [37]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [37])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_36  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [36]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [36])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_35  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [35]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [35])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_34  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [34]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [34])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_33  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [33]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [33])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_32  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [32]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [32])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_31  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [31]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [31])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_30  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [30]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [30])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_29  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [29]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [29])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_28  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [28]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [28])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_27  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [27]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [27])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_26  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [26]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [26])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_25  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [25]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [25])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_24  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [24]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [24])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_23  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [23]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [23])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_22  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [22]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [22])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_21  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [21]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [21])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_20  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [20]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [20])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_19  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [19]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [19])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_18  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [18]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [18])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_17  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [17]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [17])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_16  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [16]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [16])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_15  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [15]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [15])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_14  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [14]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [14])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_13  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [13]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [13])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_12  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [12]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [12])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_11  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [11]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [11])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_10  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [10]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [10])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_9  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [9]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [9])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_8  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [8]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [8])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_7  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [7]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [7])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_6  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [6]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [6])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_5  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [5]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [5])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_4  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [4]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [4])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_3  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [3]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [3])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_2  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [2]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [2])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_1  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [1]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [1])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2_0  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg [0]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [0])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1_7  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg [7]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [7])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1_6  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg [6]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [6])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1_5  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg [5]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [5])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1_4  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg [4]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [4])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1_3  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg [3]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [3])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1_2  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg [2]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [2])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1_1  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg [1]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [1])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1_0  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg [0]),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [0])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel_1  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Result [1]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/reset_tx_test_en_OR_183_o ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel_0  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Maccum_tx_test_patt_seed_sel_lut [0]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/reset_tx_test_en_OR_183_o ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count_6  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Result [6]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/reset_tx_test_en_OR_183_o ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count [6])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count_5  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Result [5]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/reset_tx_test_en_OR_183_o ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count [5])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count_4  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Result [4]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/reset_tx_test_en_OR_183_o ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count [4])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count_3  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Result [3]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/reset_tx_test_en_OR_183_o ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count [3])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count_2  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Result [2]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/reset_tx_test_en_OR_183_o ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count [2])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count_1  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Result<1>1 ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/reset_tx_test_en_OR_183_o ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count [1])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count_0  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Result<0>1 ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/reset_tx_test_en_OR_183_o ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count [0])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_57  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<57> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [57])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_56  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<56> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [56])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_55  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<55> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [55])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_54  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<54> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [54])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_53  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<53> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [53])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_52  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<52> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [52])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_51  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<51> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [51])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_50  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<50> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [50])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_49  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<49> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [49])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_48  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<48> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [48])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_47  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<47> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [47])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_46  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<46> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [46])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_45  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<45> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [45])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_44  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<44> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [44])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_43  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<43> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [43])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_42  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<42> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [42])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_41  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<41> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [41])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_40  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<40> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [40])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_39  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<39> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [39])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_38  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<38> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [38])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_37  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<37> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [37])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_36  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<36> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [36])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_35  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<35> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [35])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_34  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<34> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [34])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_33  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<33> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [33])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_32  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<32> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [32])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_31  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<31> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [31])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_30  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<30> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [30])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_29  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<29> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [29])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_28  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<28> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [28])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_27  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<27> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [27])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_26  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<26> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [26])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_25  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<25> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [25])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_24  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<24> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [24])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_23  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<23> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [23])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_22  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<22> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [22])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_21  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<21> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [21])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_20  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<20> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [20])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_19  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<19> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [19])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_18  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<18> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [18])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_17  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<17> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [17])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_16  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<16> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [16])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_15  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<15> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [15])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_14  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<14> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [14])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_13  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<13> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [13])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_12  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<12> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [12])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_11  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<11> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [11])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_10  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<10> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [10])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_9  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<9> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [9])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_8  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<8> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [8])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_7  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<7> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [7])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_6  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<6> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [6])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_5  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<5> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [5])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_4  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<4> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [4])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_3  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<3> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [3])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_2  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<2> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [2])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_1  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<1> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [1])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg_0  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<0> )
,
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [0])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/new_tx_test_seed  (
    .C(clk156),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count[6]_reduce_and_6_o ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/reset_tx_test_en_OR_183_o ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/new_tx_test_seed_4087 )
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd2  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/_n0043 [58]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd2_4150 )
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd3  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd3-In ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd3_4151 )
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd1  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd1-In ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd1_4149 )
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_65  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<65> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [65])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_64  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<64> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [64])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_63  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<63> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [63])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_62  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<62> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [62])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_61  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<61> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [61])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_60  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<60> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [60])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_59  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<59> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [59])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_58  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<58> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [58])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_57  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<57> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [57])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_56  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<56> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [56])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_55  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<55> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [55])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_54  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<54> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [54])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_53  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<53> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [53])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_52  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<52> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [52])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_51  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<51> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [51])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_50  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<50> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [50])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_49  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<49> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [49])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_48  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<48> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [48])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_47  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<47> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [47])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_46  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<46> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [46])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_45  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<45> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [45])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_44  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<44> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [44])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_43  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<43> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [43])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_42  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<42> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [42])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_41  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<41> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [41])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_40  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<40> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [40])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_39  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<39> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [39])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_38  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<38> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [38])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_37  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<37> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [37])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_36  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<36> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [36])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_35  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<35> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [35])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_34  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<34> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [34])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_33  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<33> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [33])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_32  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<32> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [32])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_31  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<31> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [31])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_30  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<30> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [30])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_29  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<29> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [29])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_28  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<28> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [28])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_27  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<27> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [27])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_26  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<26> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [26])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_25  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<25> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [25])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_24  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<24> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [24])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_23  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<23> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [23])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_22  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<22> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [22])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_21  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<21> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [21])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_20  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<20> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [20])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_19  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<19> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [19])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_18  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<18> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [18])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_17  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<17> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [17])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_16  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<16> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [16])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_15  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<15> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [15])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_14  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<14> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [14])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_13  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<13> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [13])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_12  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<12> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [12])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_11  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<11> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [11])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_10  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<10> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [10])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_9  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<9> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [9])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_8  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<8> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [8])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_7  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<7> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [7])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_6  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<6> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [6])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_5  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<5> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [5])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_4  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<4> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [4])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_3  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<3> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [3])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_2  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<2> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [2])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_1  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<1> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [1])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_0  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<0> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [0])
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/signal_ok_reg  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_5/d ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/signal_ok_reg_4222 )
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_6  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rxreset_local_430 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_6_4223 )
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_1  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rxreset_local_430 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_1_4221 )
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rxreset_local_430 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 )
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_3  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rxreset_local_430 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_3_4226 )
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rxreset_local_430 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 )
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rxreset_local_430 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4227 )
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt_4  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt4 ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_194_o ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [4])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt_3  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt3 ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_194_o ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [3])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt_2  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt2 ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_194_o ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [2])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt_1  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt1 ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_194_o ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [1])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt_0  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_194_o ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [0])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1-In_4395 ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_194_o ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1_4422 )
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2-In ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_194_o ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2_4393 )
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3-In ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_194_o ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3_4394 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt_6  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0142_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt[6]_GND_26_o_mux_32_OUT<6> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [6])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt_5  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0142_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt[6]_GND_26_o_mux_32_OUT<5> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [5])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt_4  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0142_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt[6]_GND_26_o_mux_32_OUT<4> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [4])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt_3  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0142_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt[6]_GND_26_o_mux_32_OUT<3> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [3])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt_2  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0142_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt[6]_GND_26_o_mux_32_OUT<2> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [2])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt_1  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0142_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt[6]_GND_26_o_mux_32_OUT<1> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [1])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt_0  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0142_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt[6]_GND_26_o_mux_32_OUT<0> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [0])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt_4  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0174_inv_4399 ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt[4]_GND_26_o_mux_33_OUT<4> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [4])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt_3  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0174_inv_4399 ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt[4]_GND_26_o_mux_33_OUT<3> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [3])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt_2  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0174_inv_4399 ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt[4]_GND_26_o_mux_33_OUT<2> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [2])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt_1  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0174_inv_4399 ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt[4]_GND_26_o_mux_33_OUT<1> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [1])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt_0  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0174_inv_4399 ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt[4]_GND_26_o_mux_33_OUT<0> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [0])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt[4]_GND_26_o_MUX_394_o ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_194_o ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_4420 )
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_int ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_194_o ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_555 )
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/test_sh  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state[2]_GND_26_o_Mux_27_o ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_194_o ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/test_sh_4421 )
  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_xor<15>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<14>_4428 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<15> )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<15> )
  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_xor<14>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<13>_4430 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<14> )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<14> )
  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<14>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<13>_4430 )
,
    .DI(N0),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<14> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<14>_4428 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_xor<13>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<12>_4432 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<13> )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<13> )
  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<13>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<12>_4432 )
,
    .DI(N0),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<13> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<13>_4430 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_xor<12>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<11>_4434 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<12> )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<12> )
  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<12>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<11>_4434 )
,
    .DI(N0),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<12> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<12>_4432 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_xor<11>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<10>_4436 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<11> )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<11> )
  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<11>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<10>_4436 )
,
    .DI(N0),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<11> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<11>_4434 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_xor<10>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<9>_4438 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<10> )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<10> )
  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<10>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<9>_4438 )
,
    .DI(N0),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<10> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<10>_4436 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_xor<9>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<8>_4440 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<9> ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<9> )
  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<9>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<8>_4440 )
,
    .DI(N0),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<9> ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<9>_4438 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_xor<8>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<7>_4442 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<8> ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<8> )
  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<8>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<7>_4442 )
,
    .DI(N0),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<8> ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<8>_4440 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_xor<7>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<6>_4444 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<7> ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<7> )
  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<7>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<6>_4444 )
,
    .DI(N0),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<7> ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<7>_4442 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_xor<6>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<5>_4446 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<6> ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<6> )
  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<6>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<5>_4446 )
,
    .DI(N0),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<6> ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<6>_4444 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_xor<5>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<4>_4448 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<5> ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<5> )
  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<5>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<4>_4448 )
,
    .DI(N0),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<5> ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<5>_4446 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_xor<4>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<3>_4450 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<4> ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<4> )
  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<4>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<3>_4450 )
,
    .DI(N0),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<4> ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<4>_4448 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_xor<3>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<2>_4452 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<3> ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<3> )
  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<3>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<2>_4452 )
,
    .DI(N0),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<3> ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<3>_4450 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_xor<2>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<1>_4454 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<2> ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<2> )
  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<2>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<1>_4454 )
,
    .DI(N0),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<2> ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<2>_4452 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_xor<1>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<0>_4456 )
,
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<1> ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<1> )
  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<1>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<0>_4456 )
,
    .DI(N0),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<1> ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<1>_4454 )

  );
  XORCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_xor<0>  (
    .CI(N0),
    .LI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<0>_rt_5756 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<0> )
  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<0>  (
    .CI(N0),
    .DI(NlwRenamedSig_OI_drp_dwe),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<0>_rt_5756 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<0>_4456 )

  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt_4  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/_n0120_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mcount_ber_cnt4 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt [4])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt_3  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/_n0120_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mcount_ber_cnt3 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt [3])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt_2  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/_n0120_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mcount_ber_cnt2 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt [2])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt_1  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/_n0120_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mcount_ber_cnt1 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt [1])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt_0  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/_n0120_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mcount_ber_cnt ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt [0])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1-In ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4227 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4510 )
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2-In_4465 ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4227 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 )
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4227 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 )
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_count_inc  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state[2]_GND_27_o_Mux_27_o ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4227 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_count_inc_551 )
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_test_sh  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state[2]_GND_27_o_Mux_25_o ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4227 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_test_sh_4485 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us_15  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/_n0099_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<15> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [15])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us_14  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/_n0099_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<14> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [14])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us_13  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/_n0099_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<13> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [13])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us_12  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/_n0099_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<12> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [12])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us_11  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/_n0099_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<11> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [11])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us_10  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/_n0099_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<10> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [10])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us_9  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/_n0099_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<9> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [9])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us_8  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/_n0099_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<8> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [8])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us_7  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/_n0099_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<7> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [7])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us_6  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/_n0099_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<6> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [6])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us_5  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/_n0099_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<5> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [5])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us_4  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/_n0099_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<4> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [4])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us_3  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/_n0099_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<3> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [3])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us_2  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/_n0099_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<2> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [2])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us_1  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/_n0099_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<1> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [1])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us_0  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/_n0099_inv ),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<0> )
,
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [0])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_57  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [8]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [57])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_56  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [9]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [56])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_55  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [10]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [55])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_54  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [11]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [54])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_53  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [12]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [53])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_52  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [13]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [52])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_51  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [14]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [51])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_50  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [15]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [50])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_49  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [16]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [49])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_48  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [17]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [48])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_47  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [18]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [47])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_46  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [19]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [46])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_45  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [20]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [45])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_44  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [21]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [44])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_43  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [22]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [43])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_42  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [23]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [42])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_41  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [24]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [41])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_40  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [25]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [40])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_39  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [26]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [39])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_38  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [27]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [38])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_37  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [28]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [37])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_36  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [29]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [36])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_35  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [30]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [35])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_34  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [31]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [34])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_33  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [32]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [33])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_32  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [33]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [32])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_31  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [34]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [31])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_30  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [35]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [30])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_29  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [36]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [29])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_28  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [37]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [28])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_27  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [38]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [27])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_26  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [39]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [26])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_25  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [40]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [25])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_24  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [41]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [24])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_23  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [42]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [23])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_22  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [43]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [22])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_21  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [44]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [21])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_20  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [45]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [20])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_19  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [46]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [19])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_18  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [47]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [18])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_17  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [48]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [17])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_16  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [49]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [16])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_15  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [50]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [15])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_14  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [51]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [14])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_13  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [52]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [13])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_12  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [53]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [12])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_11  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [54]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [11])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_10  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [55]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [10])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_9  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [56]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [9])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_8  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [57]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [8])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_7  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [58]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [7])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_6  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [59]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [6])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_5  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [60]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [5])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_4  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [61]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [4])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_3  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [62]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [3])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_2  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [63]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [2])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_1  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [64]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [1])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg_0  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [65]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4_4225 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [0])
  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<11>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<10>_4587 )
,
    .DI(N0),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<11>_4586 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/rx_66_enc[65]_expected_data[63]_not_equal_7_o )
  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<10>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<9>_4589 )
,
    .DI(N0),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<10>_4588 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<10>_4587 )

  );
  LUT6 #(
    .INIT ( 64'h0001000000000001 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<10>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [57]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [59]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [60]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [61]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/expected_data [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [58]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<10>_4588 )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<9>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<8>_4591 )
,
    .DI(N0),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<9>_4590 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<9>_4589 )

  );
  LUT6 #(
    .INIT ( 64'h0000000000000001 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<9>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [51]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [52]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [53]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [54]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [55]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [56]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<9>_4590 )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<8>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<7>_4593 )
,
    .DI(N0),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<8>_4592 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<8>_4591 )

  );
  LUT6 #(
    .INIT ( 64'h0000000000000001 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<8>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [45]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [46]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [47]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [48]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [49]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [50]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<8>_4592 )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<7>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<6>_4595 )
,
    .DI(N0),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<7>_4594 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<7>_4593 )

  );
  LUT6 #(
    .INIT ( 64'h0000000000000001 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<7>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [39]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [40]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [41]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [42]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [43]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [44]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<7>_4594 )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<6>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<5>_4597 )
,
    .DI(N0),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<6>_4596 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<6>_4595 )

  );
  LUT6 #(
    .INIT ( 64'h0000000000000001 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<6>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [33]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [34]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [35]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [36]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [37]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [38]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<6>_4596 )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<5>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<4>_4599 )
,
    .DI(N0),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<5>_4598 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<5>_4597 )

  );
  LUT6 #(
    .INIT ( 64'h0000000000000001 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<5>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [27]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [28]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [29]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [30]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [31]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [32]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<5>_4598 )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<4>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<3>_4601 )
,
    .DI(N0),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<4>_4600 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<4>_4599 )

  );
  LUT6 #(
    .INIT ( 64'h0001000000000001 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<4>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [22]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [23]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [24]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [25]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [26]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/expected_data [0]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<4>_4600 )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<3>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<2>_4603 )
,
    .DI(N0),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<3>_4602 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<3>_4601 )

  );
  LUT6 #(
    .INIT ( 64'h0000000000000001 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<3>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [16]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [17]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [18]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [19]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [20]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [21]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<3>_4602 )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<2>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<1>_4605 )
,
    .DI(N0),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<2>_4604 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<2>_4603 )

  );
  LUT6 #(
    .INIT ( 64'h0000000000000001 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<2>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [10]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [11]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [12]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [13]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [14]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [15]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<2>_4604 )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<1>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<0>_4607 )
,
    .DI(N0),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<1> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<1>_4605 )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<0>  (
    .CI(NlwRenamedSig_OI_drp_dwe),
    .DI(N0),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<0> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_cy<0>_4607 )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<21>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<20>_4616 )
,
    .DI(N0),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [65]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/rx_66_enc[65]_expected_data[63]_not_equal_9_o )
  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<20>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<19>_4618 )
,
    .DI(N0),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<20> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<20>_4616 )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<19>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<18>_4620 )
,
    .DI(N0),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<19> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<19>_4618 )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<18>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<17>_4622 )
,
    .DI(N0),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<18> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<18>_4620 )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<17>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<16>_4624 )
,
    .DI(N0),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<17> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<17>_4622 )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<16>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<15>_4626 )
,
    .DI(N0),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<16> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<16>_4624 )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<15>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<14>_4628 )
,
    .DI(N0),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<15> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<15>_4626 )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<14>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<13>_4630 )
,
    .DI(N0),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<14> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<14>_4628 )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<13>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<12>_4632 )
,
    .DI(N0),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<13> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<13>_4630 )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<12>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<11>_4634 )
,
    .DI(N0),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<12> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<12>_4632 )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<11>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<10>_4636 )
,
    .DI(N0),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<11> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<11>_4634 )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<10>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<9>_4638 )
,
    .DI(N0),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<10> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<10>_4636 )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<9>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<8>_4640 )
,
    .DI(N0),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<9> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<9>_4638 )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<8>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<7>_4642 )
,
    .DI(N0),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<8> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<8>_4640 )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<7>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<6>_4644 )
,
    .DI(N0),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<7> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<7>_4642 )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<6>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<5>_4646 )
,
    .DI(N0),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<6> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<6>_4644 )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<5>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<4>_4648 )
,
    .DI(N0),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<5> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<5>_4646 )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<4>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<3>_4650 )
,
    .DI(N0),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<4> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<4>_4648 )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<3>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<2>_4652 )
,
    .DI(N0),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<3> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<3>_4650 )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<2>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<1>_4654 )
,
    .DI(N0),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<2> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<2>_4652 )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<1>  (
    .CI
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<0>_4656 )
,
    .DI(N0),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<1> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<1>_4654 )

  );
  MUXCY 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<0>  (
    .CI(NlwRenamedSig_OI_drp_dwe),
    .DI(N0),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<0> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_cy<0>_4656 )

  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count_6  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Result [6]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_3_4226 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [6])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count_5  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Result [5]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_3_4226 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [5])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count_4  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Result [4]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_3_4226 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [4])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count_3  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Result [3]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_3_4226 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [3])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count_2  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Result [2]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_3_4226 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [2])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count_1  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Result [1]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_3_4226 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [1])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count_0  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Result [0]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_3_4226 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [0])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/err_block_count_inc_out  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/err_block_count_inc_in_GND_28_o_MUX_424_o ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_3_4226 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/err_block_count_inc_out_554 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_63  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<63> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [63])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_62  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<62> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [62])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_61  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<61> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [61])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_60  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<60> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [60])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_59  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<59> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [59])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_58  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<58> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [58])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_57  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<57> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [57])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_56  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<56> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [56])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_55  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<55> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [55])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_54  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<54> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [54])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_53  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<53> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [53])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_52  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<52> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [52])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_51  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<51> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [51])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_50  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<50> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [50])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_49  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<49> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [49])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_48  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<48> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [48])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_47  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<47> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [47])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_46  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<46> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [46])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_45  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<45> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [45])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_44  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<44> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [44])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_43  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<43> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [43])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_42  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<42> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [42])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_41  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<41> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [41])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_40  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<40> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [40])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_39  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<39> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [39])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_38  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<38> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [38])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_37  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<37> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [37])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_36  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<36> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [36])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_35  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<35> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [35])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_34  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<34> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [34])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_33  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<33> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [33])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_32  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<32> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [32])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_31  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<31> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [31])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_30  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<30> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [30])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_29  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<29> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [29])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_28  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<28> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [28])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_27  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<27> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [27])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_26  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<26> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [26])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_25  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<25> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [25])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_24  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<24> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [24])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_23  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<23> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [23])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_22  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<22> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [22])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_21  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<21> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [21])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_20  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<20> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [20])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_19  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<19> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [19])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_18  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<18> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [18])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_17  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<17> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [17])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_16  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<16> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [16])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_15  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<15> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [15])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_14  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<14> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [14])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_13  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<13> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [13])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_12  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<12> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [12])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_11  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<11> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [11])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_10  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<10> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [10])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_9  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<9> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [9])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_8  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<8> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [8])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_7  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<7> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [7])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_6  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<6> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [6])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_5  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<5> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [5])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_4  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<4> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [4])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_3  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<3> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [3])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_2  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<2> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [2])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_1  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<1> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [1])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out_0  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<0> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [0])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg_2  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg[2]_GND_30_o_mux_145_OUT<2> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [2])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg_1  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg[2]_GND_30_o_mux_145_OUT<1> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [1])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg_0  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg[2]_GND_30_o_mux_145_OUT<0> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [0])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_7  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c7[6]_mux_272_OUT<7> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_7_4996 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_6  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c7[6]_mux_272_OUT<6> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_6_4995 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_5  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c7[6]_mux_272_OUT<5> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_5_4994 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_4  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c7[6]_mux_272_OUT<4> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_4_4993 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_3  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c7[6]_mux_272_OUT<3> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_3_4992 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_1  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c7[6]_mux_272_OUT<1> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_1_4991 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_0  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c7[6]_mux_272_OUT<0> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_0_4990 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_7  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c6[6]_mux_261_OUT<7> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_7_4989 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_6  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c6[6]_mux_261_OUT<6> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_6_4988 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_5  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c6[6]_mux_261_OUT<5> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_5_4987 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_4  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c6[6]_mux_261_OUT<4> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_4_4986 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_3  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c6[6]_mux_261_OUT<3> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_3_4985 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_1  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c6[6]_mux_261_OUT<1> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_1_4984 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_0  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c6[6]_mux_261_OUT<0> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_0_4983 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_7  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c5[6]_mux_250_OUT<7> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_7_4982 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_6  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c5[6]_mux_250_OUT<6> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_6_4981 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_5  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c5[6]_mux_250_OUT<5> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_5_4980 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_4  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c5[6]_mux_250_OUT<4> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_4_4979 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_3  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c5[6]_mux_250_OUT<3> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_3_4978 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_1  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c5[6]_mux_250_OUT<1> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_1_4977 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_0  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c5[6]_mux_250_OUT<0> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_0_4976 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_7  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c4[6]_mux_239_OUT<7> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_7_4975 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_6  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c4[6]_mux_239_OUT<6> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_6_4974 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_5  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c4[6]_mux_239_OUT<5> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_5_4973 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_4  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c4[6]_mux_239_OUT<4> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_4_4972 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_3  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c4[6]_mux_239_OUT<3> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_3_4971 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_1  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c4[6]_mux_239_OUT<1> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_1_4970 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_0  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c4[6]_mux_239_OUT<0> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_0_4969 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_7  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c3[6]_mux_228_OUT<7> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_7_4968 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_6  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c3[6]_mux_228_OUT<6> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_6_4967 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_5  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c3[6]_mux_228_OUT<5> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_5_4966 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_4  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c3[6]_mux_228_OUT<4> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_4_4965 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_3  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c3[6]_mux_228_OUT<3> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_3_4964 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_1  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c3[6]_mux_228_OUT<1> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_1_4963 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_0  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c3[6]_mux_228_OUT<0> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_0_4962 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_7  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c2[6]_mux_217_OUT<7> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_7_4961 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_6  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c2[6]_mux_217_OUT<6> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_6_4960 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_5  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c2[6]_mux_217_OUT<5> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_5_4959 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_4  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c2[6]_mux_217_OUT<4> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_4_4958 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_3  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c2[6]_mux_217_OUT<3> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_3_4957 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_1  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c2[6]_mux_217_OUT<1> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_1_4956 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_0  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c2[6]_mux_217_OUT<0> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_0_4955 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_7  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c1[6]_mux_206_OUT<7> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_7_4954 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_6  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c1[6]_mux_206_OUT<6> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_6_4953 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_5  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c1[6]_mux_206_OUT<5> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_5_4952 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_4  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c1[6]_mux_206_OUT<4> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_4_4951 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_3  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c1[6]_mux_206_OUT<3> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_3_4950 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_1  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c1[6]_mux_206_OUT<1> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_1_4949 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_0  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c1[6]_mux_206_OUT<0> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_0_4948 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_7  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c0[6]_mux_195_OUT<7> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_7_4947 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_6  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c0[6]_mux_195_OUT<6> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_6_4946 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_5  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c0[6]_mux_195_OUT<5> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_5_4945 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_4  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c0[6]_mux_195_OUT<4> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_4_4944 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_3  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c0[6]_mux_195_OUT<3> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_3_4943 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_1  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c0[6]_mux_195_OUT<1> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_1_4942 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_0  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c0[6]_mux_195_OUT<0> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_0_4941 )
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out_7  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out[7]_GND_30_o_mux_323_OUT<7> ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1078 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out [7])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out_6  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out[7]_GND_30_o_mux_323_OUT<6> ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1078 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out [6])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out_5  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out[7]_GND_30_o_mux_323_OUT<5> ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1078 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out [5])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out_4  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out[7]_GND_30_o_mux_323_OUT<4> ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1078 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out [4])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out_3  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out[7]_GND_30_o_mux_323_OUT<3> ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1078 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out [3])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out_2  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out[7]_GND_30_o_mux_323_OUT<2> ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1078 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out [2])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out_1  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out[7]_GND_30_o_mux_323_OUT<1> ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1078 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out [1])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out_0  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out[7]_GND_30_o_mux_323_OUT<0> ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1078 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out [0])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next_reg_2  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next_reg[2]_GND_30_o_mux_182_OUT<2> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next_reg [2])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next_reg_1  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next_reg[2]_GND_30_o_mux_182_OUT<1> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next_reg [1])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next_reg_0  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next_reg[2]_GND_30_o_mux_182_OUT<0> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next_reg [0])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_65  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [65]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [65])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_64  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [64]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [64])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_63  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [63]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [63])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_62  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [62]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [62])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_61  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [61]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [61])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_60  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [60]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [60])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_59  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [59]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [59])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_58  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [58]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [58])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_57  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [57]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [57])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_56  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [56]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [56])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_55  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [55]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [55])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_54  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [54]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [54])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_53  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [53]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [53])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_52  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [52]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [52])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_51  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [51]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [51])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_50  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [50]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [50])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_49  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [49]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [49])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_48  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [48]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [48])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_47  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [47]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [47])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_46  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [46]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [46])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_45  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [45]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [45])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_44  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [44]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [44])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_43  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [43]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [43])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_42  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [42]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [42])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_41  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [41]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [41])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_40  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [40]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [40])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_39  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [39]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [39])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_38  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [38]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [38])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_37  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [37]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [37])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_36  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [36]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [36])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_35  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [35]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [35])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_34  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [34]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [34])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_33  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [33]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [33])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_32  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [32]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [32])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_31  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [31]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [31])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_30  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [30]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [30])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_29  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [29]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [29])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_28  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [28]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [28])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_27  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [27]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [27])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_26  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [26]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [26])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_25  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [25]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [25])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_24  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [24]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [24])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_23  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [23]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [23])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_22  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [22]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [22])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_21  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [21]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [21])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_20  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [20]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [20])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_19  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [19]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [19])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_18  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [18]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [18])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_17  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [17]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [17])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_16  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [16]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [16])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_15  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [15]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [15])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_14  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [14]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [14])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_13  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [13]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [13])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_12  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [12]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [12])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_11  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [11]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [11])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_10  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [10]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [10])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_9  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [9]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [9])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_8  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [8]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [8])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_7  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [7]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [7])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_6  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [6]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [6])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_5  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [5]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [5])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_4  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [4]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [4])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_3  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [3]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [3])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_2  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [2]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [2])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_1  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [1]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [1])
  );
  FDRE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg_0  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [0]),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [0])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd1  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd1-In_5070 ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_6_4223 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd1_5067 )
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2-In_5071 ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_6_4223 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2_5068 )
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3-In ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_6_4223 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5069 )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl_7  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT<7> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl [7])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl_6  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT<6> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl [6])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl_5  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT<5> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl [5])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl_4  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT<4> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl [4])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl_3  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT<3> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl [3])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl_2  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT<2> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl [2])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl_1  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT<1> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl [1])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl_0  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT<0> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl [0])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_63  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<63> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [63])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_62  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<62> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [62])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_61  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<61> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [61])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_60  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<60> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [60])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_59  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<59> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [59])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_58  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<58> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [58])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_57  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<57> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [57])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_56  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<56> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [56])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_55  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<55> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [55])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_54  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<54> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [54])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_53  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<53> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [53])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_52  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<52> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [52])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_51  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<51> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [51])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_50  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<50> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [50])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_49  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<49> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [49])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_48  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<48> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [48])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_47  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<47> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [47])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_46  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<46> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [46])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_45  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<45> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [45])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_44  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<44> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [44])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_43  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<43> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [43])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_42  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<42> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [42])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_41  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<41> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [41])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_40  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<40> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [40])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_39  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<39> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [39])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_38  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<38> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [38])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_37  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<37> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [37])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_36  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<36> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [36])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_35  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<35> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [35])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_34  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<34> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [34])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_33  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<33> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [33])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_32  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<32> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [32])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_31  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<31> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [31])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_30  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<30> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [30])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_29  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<29> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [29])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_28  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<28> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [28])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_27  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<27> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [27])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_26  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<26> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [26])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_25  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<25> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [25])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_24  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<24> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [24])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_23  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<23> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [23])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_22  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<22> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [22])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_21  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<21> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [21])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_20  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<20> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [20])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_19  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<19> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [19])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_18  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<18> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [18])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_17  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<17> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [17])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_16  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<16> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [16])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_15  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<15> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [15])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_14  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<14> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [14])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_13  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<13> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [13])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_12  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<12> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [12])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_11  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<11> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [11])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_10  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<10> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [10])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_9  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<9> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [9])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_8  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<8> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [8])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_7  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<7> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [7])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_6  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<6> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [6])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_5  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<5> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [5])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_4  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<4> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [4])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_3  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<3> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [3])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_2  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<2> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [2])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_1  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<1> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [1])
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_0  (
    .C(rxusrclk2),
    .CE(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv ),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<0> ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [0])
  );
  LUT5 #(
    .INIT ( 32'h00000008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_test_mode_int_pcs_rxreset_AND_376_o1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[0].synch_inst/q_540 ),
    .I1(\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/q ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/q_543 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resets_resyncs_i/resynch[0].synch_inst/q_539 ),
    .I4(rxreset322),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_test_mode_int_pcs_rxreset_AND_376_o )
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/Mmux_d1_d_MUX_806_o11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/d1_275 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/d1_d_MUX_806_o )
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/Mmux_d1_d_MUX_806_o11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/d1_278 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/d1_d_MUX_806_o )
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/Mmux_d1_d_MUX_806_o11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/d1_281 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o )
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd110  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [0]),
    .O(xgmii_rxd[0])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd210  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [10]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [10]),
    .O(xgmii_rxd[10])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd310  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [11]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [11]),
    .O(xgmii_rxd[11])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd410  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [12]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [12]),
    .O(xgmii_rxd[12])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd510  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [13]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [13]),
    .O(xgmii_rxd[13])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd65  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [14]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [14]),
    .O(xgmii_rxd[14])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd71  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [15]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [15]),
    .O(xgmii_rxd[15])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd81  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [16]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [16]),
    .O(xgmii_rxd[16])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd91  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [17]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [17]),
    .O(xgmii_rxd[17])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd101  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [18]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [18]),
    .O(xgmii_rxd[18])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd111  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [19]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [19]),
    .O(xgmii_rxd[19])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd121  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [1]),
    .O(xgmii_rxd[1])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd131  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [20]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [20]),
    .O(xgmii_rxd[20])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd141  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [21]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [21]),
    .O(xgmii_rxd[21])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd151  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [22]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [22]),
    .O(xgmii_rxd[22])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd161  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [23]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [23]),
    .O(xgmii_rxd[23])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd171  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [24]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [24]),
    .O(xgmii_rxd[24])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd181  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [25]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [25]),
    .O(xgmii_rxd[25])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd191  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [26]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [26]),
    .O(xgmii_rxd[26])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd201  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [27]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [27]),
    .O(xgmii_rxd[27])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd211  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [28]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [28]),
    .O(xgmii_rxd[28])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd221  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [29]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [29]),
    .O(xgmii_rxd[29])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd231  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [2]),
    .O(xgmii_rxd[2])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd241  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [30]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [30]),
    .O(xgmii_rxd[30])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd251  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [31]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [31]),
    .O(xgmii_rxd[31])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd261  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [32]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [32]),
    .O(xgmii_rxd[32])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd271  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [33]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [33]),
    .O(xgmii_rxd[33])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd281  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [34]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [34]),
    .O(xgmii_rxd[34])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd291  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [35]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [35]),
    .O(xgmii_rxd[35])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd301  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [36]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [36]),
    .O(xgmii_rxd[36])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd311  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [37]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [37]),
    .O(xgmii_rxd[37])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd321  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [38]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [38]),
    .O(xgmii_rxd[38])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd331  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [39]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [39]),
    .O(xgmii_rxd[39])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd341  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [3]),
    .O(xgmii_rxd[3])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd351  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [40]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [40]),
    .O(xgmii_rxd[40])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd361  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [41]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [41]),
    .O(xgmii_rxd[41])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd371  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [42]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [42]),
    .O(xgmii_rxd[42])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd381  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [43]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [43]),
    .O(xgmii_rxd[43])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd391  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [44]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [44]),
    .O(xgmii_rxd[44])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd401  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [45]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [45]),
    .O(xgmii_rxd[45])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd411  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [46]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [46]),
    .O(xgmii_rxd[46])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd421  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [47]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [47]),
    .O(xgmii_rxd[47])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd431  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [48]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [48]),
    .O(xgmii_rxd[48])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd441  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [49]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [49]),
    .O(xgmii_rxd[49])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd451  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [4]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [4]),
    .O(xgmii_rxd[4])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd461  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [50]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [50]),
    .O(xgmii_rxd[50])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd471  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [51]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [51]),
    .O(xgmii_rxd[51])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd481  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [52]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [52]),
    .O(xgmii_rxd[52])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd491  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [53]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [53]),
    .O(xgmii_rxd[53])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd501  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [54]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [54]),
    .O(xgmii_rxd[54])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd511  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [55]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [55]),
    .O(xgmii_rxd[55])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd521  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [56]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [56]),
    .O(xgmii_rxd[56])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd531  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [57]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [57]),
    .O(xgmii_rxd[57])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd541  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [58]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [58]),
    .O(xgmii_rxd[58])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd551  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [59]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [59]),
    .O(xgmii_rxd[59])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd561  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [5]),
    .O(xgmii_rxd[5])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd571  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [60]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [60]),
    .O(xgmii_rxd[60])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd581  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [61]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [61]),
    .O(xgmii_rxd[61])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd591  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [62]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [62]),
    .O(xgmii_rxd[62])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd601  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [63]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [63]),
    .O(xgmii_rxd[63])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd611  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [6]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [6]),
    .O(xgmii_rxd[6])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd621  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [7]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [7]),
    .O(xgmii_rxd[7])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd631  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [8]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [8]),
    .O(xgmii_rxd[8])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxd641  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/data_out [9]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2 [9]),
    .O(xgmii_rxd[9])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxc11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/ctrl_out [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg2 [0]),
    .O(xgmii_rxc[0])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxc21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/ctrl_out [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg2 [1]),
    .O(xgmii_rxc[1])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxc31  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/ctrl_out [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg2 [2]),
    .O(xgmii_rxc[2])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxc41  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/ctrl_out [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg2 [3]),
    .O(xgmii_rxc[3])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxc51  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/ctrl_out [4]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg2 [4]),
    .O(xgmii_rxc[4])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxc61  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/ctrl_out [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg2 [5]),
    .O(xgmii_rxc[5])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxc71  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/ctrl_out [6]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg2 [6]),
    .O(xgmii_rxc[6])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_xgmii_rxc81  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/ctrl_out [7]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/xgmii_txc_reg2 [7]),
    .O(xgmii_rxc[7])
  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_gt_txc_mux<0>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txc_mux [0])
  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/Mmux_gt_txc_mux<1>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/q_544 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_txc_mux [1])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/Mmux_q_d1_MUX_807_o11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ),
    .I1(\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/q ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/d1_272 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/q_d1_MUX_807_o )
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/Mmux_d1_d_MUX_806_o11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/d1_272 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/prbs31_rx_enable_core_reg_546 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/d1_d_MUX_806_o )
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/Mmux_q_d1_MUX_807_o11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/q_543 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/d1_275 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/q_d1_MUX_807_o )
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/Mmux_q_d1_MUX_807_o11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/q_541 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/d1_281 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/q_d1_MUX_807_o )
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/Mmux_q_d1_MUX_807_o11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/q_542 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/d1_278 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/q_d1_MUX_807_o )
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[0].synch_inst/Mmux_q_d1_MUX_807_o11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[0].synch_inst/q_540 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[0].synch_inst/d1_284 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[0].synch_inst/q_d1_MUX_807_o )
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[0].synch_inst/Mmux_d1_d_MUX_806_o11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[0].synch_inst/d1_284 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clear_test_pattern_err_count_reg_545 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[0].synch_inst/d1_d_MUX_806_o )
  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_reset_clear_core_int1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_reset_clear_core_intr_547 ),
    .I1(resetdone),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_reset_clear_core_int )
  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_rxreset1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resets_resyncs_i/resynch[0].synch_inst/q_539 ),
    .I1(rxreset322),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_rxreset )
  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/Mmux_mdc_reg1_GND_62_o_MUX_766_o11  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_reg1_1343 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_reg1_GND_62_o_MUX_766_o )
  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/Mmux_mdc_in_GND_62_o_MUX_765_o11  (
    .I0(reset),
    .I1(mdc),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_in_GND_62_o_MUX_765_o )
  );
  LUT6 #(
    .INIT ( 64'hEEEEEEEB44444441 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mcount_bit_count_eqn_31  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count_load_en ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count_load_value [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mcount_bit_count_eqn_3 )
  );
  LUT5 #(
    .INIT ( 32'hABAB2101 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count_load_value<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1498 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3_1497 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2_1496 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1-In1 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1_1495 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count_load_value [0])
  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_just_rose_opcode[1]_AND_362_o1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_just_rose_1645 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1-In1 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1498 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3_1497 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2_1496 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1_1495 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_just_rose_opcode[1]_AND_362_o )
  );
  LUT5 #(
    .INIT ( 32'h00000800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_351_o1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/n0027 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1498 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3_1497 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2_1496 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1_1495 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_351_o )
  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_350_o1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/n0027 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1341 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1498 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3_1497 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2_1496 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1_1495 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_350_o )
  );
  LUT4 #(
    .INIT ( 16'hFFA9 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mcount_bit_count_eqn_21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count_load_en ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mcount_bit_count_eqn_2 )
  );
  LUT5 #(
    .INIT ( 32'h00000800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>31  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [1]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg[4]_GND_63_o_equal_123_o<4>1 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>3 )

  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [0]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_PWR_65_o_not_equal_135_o )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [2]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg[4]_GND_63_o_equal_123_o<4>1 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>2 )

  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFF7FFF7F7F ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [2]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg[4]_GND_63_o_equal_123_o<4>1 )
,
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_PWR_65_o_not_equal_135_o )
,
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [0]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>1_1438 )

  );
  LUT5 #(
    .INIT ( 32'h00000008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>31  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg[4]_GND_63_o_equal_123_o<4>1 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>3 )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [1]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg[4]_GND_63_o_equal_123_o<4>1 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_PWR_65_o_not_equal_132_o )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>2 )

  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFDFDFFFDF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [2]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg[4]_GND_63_o_equal_123_o<4>1 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_PWR_65_o_not_equal_132_o )
,
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [0]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1_1437 )

  );
  LUT5 #(
    .INIT ( 32'h00010000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>31  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [2]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg[4]_GND_63_o_equal_123_o<4>1 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>3 )

  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [0]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_PWR_65_o_not_equal_129_o )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [2]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg[4]_GND_63_o_equal_123_o<4>1 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>2 )

  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFEFEFFFEF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [0]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg[4]_GND_63_o_equal_123_o<4>1 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_PWR_65_o_not_equal_129_o )
,
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1_1439 )

  );
  LUT6 #(
    .INIT ( 64'hB9BBBBBBFFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_tri_int1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1498 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1_1495 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3_1497 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2_1496 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/n0027 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_tri_int )
  );
  LUT5 #(
    .INIT ( 32'h00000001 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/n0027<4>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count [4]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/n0027 )
  );
  LUT4 #(
    .INIT ( 16'hEB41 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mcount_bit_count_eqn_11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count_load_en ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count_load_value [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mcount_bit_count_eqn_1 )
  );
  LUT5 #(
    .INIT ( 32'h02020002 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad[4]_devad[4]_OR_530_o1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [4]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad[4]_devad[4]_OR_530_o )
  );
  LUT6 #(
    .INIT ( 64'h2AAA2A2A2AAAEAAA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3-In1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3_1497 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1498 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1341 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/n0027 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2_1496 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_in_reg_1632 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3-In )
  );
  LUT3 #(
    .INIT ( 8'h10 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg[4]_GND_63_o_equal_123_o<4>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [4]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [0]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg[4]_GND_63_o_equal_123_o<4>1 )

  );
  LUT4 #(
    .INIT ( 16'hFF08 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_out_int1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [15]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1_1495 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1498 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_tri_int ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_out_int )
  );
  LUT6 #(
    .INIT ( 64'hFFFFF888F888F888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<1>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [0]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>3 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1_1439 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [1]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>2 )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<1> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<1> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFF888F888F888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<9>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [8]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>3 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1_1439 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [9]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>2 )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<9> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<9> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFF888F888F888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_in_reg_1632 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>3 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1_1439 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [0]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>2 )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<0> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFF888F888F888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<2>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [1]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>3 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1_1439 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [2]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>2 )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<2> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<2> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFF888F888F888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<3>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [2]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>3 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1_1439 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [3]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>2 )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<3> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<3> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFF888F888F888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<4>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [3]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>3 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1_1439 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [4]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>2 )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<4> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<4> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFF888F888F888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<5>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [4]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>3 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1_1439 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [5]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>2 )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<5> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<5> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFF888F888F888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<6>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [5]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>3 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1_1439 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [6]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>2 )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<6> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<6> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFF888F888F888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<7>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [6]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>3 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1_1439 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [7]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>2 )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<7> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<7> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFF888F888F888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<8>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [7]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>3 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1_1439 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [8]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>2 )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<8> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<8> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFF888F888F888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<10>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [9]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>3 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1_1439 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [10]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>2 )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<10> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<10> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFF888F888F888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<11>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [10]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>3 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1_1439 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [11]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>2 )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<11> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<11> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFF888F888F888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<13>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [12]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>3 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1_1439 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [13]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>2 )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<13> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<13> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFF888F888F888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<14>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [13]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>3 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1_1439 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [14]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>2 )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<14> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<14> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFF888F888F888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<15>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [14]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>3 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1_1439 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [15]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>2 )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<15> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<15> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFF888F888F888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<12>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [11]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>3 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>1_1439 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [12]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<0>2 )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_GND_63_o_add_130_OUT<12> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_148_OUT<12> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFF888F888F888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_in_reg_1632 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>3 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [0]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>1_1438 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<0> )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>2 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFF888F888F888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<1>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [0]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>3 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [1]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>1_1438 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<1> )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>2 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<1> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFF888F888F888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<2>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [1]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>3 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [2]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>1_1438 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<2> )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>2 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<2> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFF888F888F888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<3>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [2]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>3 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [3]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>1_1438 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<3> )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>2 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<3> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFF888F888F888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<4>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [3]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>3 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [4]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>1_1438 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<4> )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>2 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<4> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFF888F888F888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<5>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [4]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>3 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [5]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>1_1438 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<5> )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>2 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<5> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFF888F888F888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<6>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [5]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>3 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [6]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>1_1438 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<6> )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>2 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<6> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFF888F888F888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<7>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [6]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>3 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [7]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>1_1438 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<7> )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>2 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<7> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFF888F888F888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<8>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [7]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>3 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [8]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>1_1438 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<8> )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>2 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<8> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFF888F888F888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<9>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [8]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>3 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [9]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>1_1438 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<9> )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>2 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<9> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFF888F888F888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<10>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [9]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>3 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [10]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>1_1438 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<10> )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>2 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<10> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFF888F888F888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<11>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [10]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>3 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [11]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>1_1438 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<11> )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>2 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<11> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFF888F888F888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<12>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [11]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>3 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [12]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>1_1438 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<12> )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>2 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<12> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFF888F888F888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<15>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [14]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>3 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [15]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>1_1438 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<15> )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>2 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<15> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFF888F888F888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<13>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [12]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>3 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [13]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>1_1438 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<13> )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>2 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<13> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFF888F888F888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<14>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [13]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>3 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [14]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>1_1438 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_GND_63_o_add_136_OUT<14> )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<0>2 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_150_OUT<14> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFF888F888F888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<1>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [0]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>3 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1_1437 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [1]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>2 )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<1> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<1> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFF888F888F888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_in_reg_1632 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>3 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1_1437 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [0]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>2 )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<0> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFF888F888F888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<2>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [1]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>3 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1_1437 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [2]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>2 )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<2> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<2> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFF888F888F888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<3>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [2]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>3 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1_1437 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [3]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>2 )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<3> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<3> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFF888F888F888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<4>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [3]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>3 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1_1437 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [4]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>2 )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<4> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<4> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFF888F888F888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<5>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [4]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>3 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1_1437 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [5]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>2 )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<5> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<5> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFF888F888F888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<6>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [5]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>3 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1_1437 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [6]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>2 )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<6> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<6> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFF888F888F888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<7>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [6]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>3 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1_1437 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [7]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>2 )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<7> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<7> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFF888F888F888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<8>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [7]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>3 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1_1437 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [8]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>2 )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<8> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<8> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFF888F888F888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<10>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [9]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>3 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1_1437 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [10]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>2 )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<10> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<10> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFF888F888F888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<11>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [10]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>3 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1_1437 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [11]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>2 )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<11> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<11> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFF888F888F888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<13>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [12]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>3 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1_1437 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [13]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>2 )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<13> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<13> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFF888F888F888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<12>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [11]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>3 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1_1437 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [12]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>2 )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<12> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<12> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFF888F888F888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<14>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [13]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>3 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1_1437 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [14]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>2 )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<14> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<14> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFF888F888F888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<9>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [8]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>3 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1_1437 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [9]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>2 )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<9> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<9> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFF888F888F888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<15>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [14]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>3 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>1_1437 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [15]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<0>2 )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_GND_63_o_add_133_OUT<15> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode[1]_devad_reg[4]_select_149_OUT<15> )

  );
  LUT4 #(
    .INIT ( 16'h8000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1-In11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/n0027 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_match_1644 ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[8]_prtad[4]_equal_89_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1-In1 )
  );
  LUT4 #(
    .INIT ( 16'h0800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/n0027 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1341 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1498 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1_1495 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_357_o )
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_devad11  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_351_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_in_reg_1632 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [0])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_devad21  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_351_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [1])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_devad31  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_351_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [2])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_devad41  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_351_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [3])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_devad51  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_351_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [4]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [3]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [4])
  );
  LUT4 #(
    .INIT ( 16'h0110 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/Mmux_drp_cs11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1673 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_cs )
  );
  LUT4 #(
    .INIT ( 16'hA3A2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1-In11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1673 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_we_rising_1339 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1-In1 )
  );
  LUT4 #(
    .INIT ( 16'h5548 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/Mmux_ipif_cs11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1673 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs )
  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_01  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1361 ),
    .I1(reset),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_0 )
  );
  LUT2 #(
    .INIT ( 4'hD ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_ipif_rnw1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_rnw )
  );
  LUT5 #(
    .INIT ( 32'h00000008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_we1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_we )
  );
  LUT5 #(
    .INIT ( 32'h00800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_we1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_we )
  );
  LUT5 #(
    .INIT ( 32'h00000800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_we1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_we )
  );
  LUT6 #(
    .INIT ( 64'h0001000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT1711  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT171 )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_42_o<15>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_42_o )
  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_40_o<15>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_40_o )
  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_8_re1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_addrdecode1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_35_o<15>1_1724 )
,
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_rnw ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_8_re )
  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_we1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_addrdecode2 ),
    .I3(NlwRenamedSig_OI_pcs_resetout),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_rnw ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode1 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_we )
  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_we1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode1 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_addrdecode2 ),
    .I3(NlwRenamedSig_OI_pcs_resetout),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_rnw ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_we )
  );
  LUT4 #(
    .INIT ( 16'h0800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_48_o<15>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_48_o<15>1 )
  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_addrdecode1 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]),
    .I3(NlwRenamedSig_OI_pcs_resetout),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_rnw ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 )
  );
  LUT6 #(
    .INIT ( 64'h8000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_re1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_rnw ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_addrdecode2 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_re )
  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_1_re1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_rnw ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_addrdecode2 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_1_re )
  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15_we1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_rnw ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_addrdecode2 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15_we )
  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_9_we1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode2 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I3
(\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15/q_0 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_rnw ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_9_we )
  );
  LUT6 #(
    .INIT ( 64'h0001000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode22  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [17]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [20]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [18]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [19]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [16]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_35_o<15>1_1724 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode2 )
  );
  LUT5 #(
    .INIT ( 32'h00000008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_addrdecode11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [17]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [16]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [20]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [18]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [19]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_addrdecode1 )
  );
  LUT3 #(
    .INIT ( 8'h20 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_we1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_we )
  );
  LUT3 #(
    .INIT ( 8'h20 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_we1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_we )
  );
  LUT3 #(
    .INIT ( 8'h10 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we )
  );
  LUT3 #(
    .INIT ( 8'h10 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_reg_1_0[15]_select_26_OUT<0>21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_reg_1_0[15]_select_26_OUT<0>2 )

  );
  LUT3 #(
    .INIT ( 8'h20 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[20]_GND_44_o_equal_101_o<20>21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1726 )

  );
  LUT3 #(
    .INIT ( 8'h10 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_PWR_46_o_equal_57_o<15>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_PWR_46_o_equal_57_o<15>1 )
  );
  LUT3 #(
    .INIT ( 8'h10 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 )
  );
  LUT3 #(
    .INIT ( 8'h80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[20]_GND_44_o_equal_101_o<20>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[20]_GND_44_o_equal_101_o<20>1 )
  );
  LUT4 #(
    .INIT ( 16'h0002 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_addrdecode21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_addrdecode1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_addrdecode2 )
  );
  LUT3 #(
    .INIT ( 8'h10 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n0397171  (
    .I0
(\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15/q_0 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [17]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [16]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039717 )
  );
  LUT3 #(
    .INIT ( 8'h20 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n0397711  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [17]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [16]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039771 )
  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/prbs31_tx_enable_core1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [4]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/prbs31_tx_enable_core_int )
  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/prbs31_rx_enable_core1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [5]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/prbs31_rx_enable_core_int )
  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_we1  (
    .I0
(\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15/q_0 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15_we ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_we )
  );
  LUT3 #(
    .INIT ( 8'hFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/_n0398<20>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [19]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [18]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [20]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/_n0398 )
  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/pcs_reset_core1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I1(reset),
    .O(NlwRenamedSig_OI_pcs_resetout)
  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/re_rising1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_15/re_prev_1998 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_re ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/re_rising )
  );
  LUT3 #(
    .INIT ( 8'h20 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_wrack_dclk1  (
    .I0(drp_drdy),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [32]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [33]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_wrack_dclk )
  );
  LUT3 #(
    .INIT ( 8'h80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rdack_dclk1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [32]),
    .I1(drp_drdy),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [33]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rdack_dclk )
  );
  LUT6 #(
    .INIT ( 64'hFD75B931EC64A820 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mmux_rd_addr2[1]_word2[33]_wide_mux_22_OUT271  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [33]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [33]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [33]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [33]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<33> )
  );
  LUT6 #(
    .INIT ( 64'hFD75B931EC64A820 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mmux_rd_addr2[1]_word2[33]_wide_mux_22_OUT261  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word1 [32]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word2 [32]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word3 [32]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/word0 [32]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2[1]_word2[33]_wide_mux_22_OUT<32> )
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1-In1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2081 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2080 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2079 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1-In )
  );
  LUT3 #(
    .INIT ( 8'h72 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2-In1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2081 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2080 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2079 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2-In )
  );
  LUT3 #(
    .INIT ( 8'h10 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0071_inv1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2080 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2079 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2081 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0071_inv )
  );
  LUT3 #(
    .INIT ( 8'h20 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0063_inv1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2080 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2079 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2081 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0063_inv )
  );
  LUT3 #(
    .INIT ( 8'h80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0059_inv1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2081 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2080 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2079 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0059_inv )
  );
  LUT3 #(
    .INIT ( 8'h20 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0067_inv1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2081 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2080 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2079 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/_n0067_inv )
  );
  LUT6 #(
    .INIT ( 64'hFD75B931EC64A820 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/Mmux_rd_addr[1]_word2[17]_wide_mux_9_OUT91  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2079 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2080 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 [17]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 [17]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 [17]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0 [17]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<17> )
  );
  LUT6 #(
    .INIT ( 64'hFD75B931EC64A820 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/Mmux_rd_addr[1]_word2[17]_wide_mux_9_OUT81  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2079 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2080 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 [16]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 [16]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 [16]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0 [16]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<16> )
  );
  LUT6 #(
    .INIT ( 64'hFD75B931EC64A820 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/Mmux_rd_addr[1]_word2[17]_wide_mux_9_OUT71  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2079 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2080 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 [15]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 [15]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 [15]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0 [15]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<15> )
  );
  LUT6 #(
    .INIT ( 64'hFD75B931EC64A820 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/Mmux_rd_addr[1]_word2[17]_wide_mux_9_OUT61  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2079 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2080 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 [14]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 [14]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 [14]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0 [14]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<14> )
  );
  LUT6 #(
    .INIT ( 64'hFD75B931EC64A820 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/Mmux_rd_addr[1]_word2[17]_wide_mux_9_OUT51  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2079 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2080 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 [13]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 [13]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 [13]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0 [13]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<13> )
  );
  LUT6 #(
    .INIT ( 64'hFD75B931EC64A820 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/Mmux_rd_addr[1]_word2[17]_wide_mux_9_OUT41  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2079 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2080 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 [12]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 [12]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 [12]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0 [12]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<12> )
  );
  LUT6 #(
    .INIT ( 64'hFD75B931EC64A820 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/Mmux_rd_addr[1]_word2[17]_wide_mux_9_OUT31  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2079 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2080 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 [11]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 [11]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 [11]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0 [11]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<11> )
  );
  LUT6 #(
    .INIT ( 64'hFD75B931EC64A820 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/Mmux_rd_addr[1]_word2[17]_wide_mux_9_OUT21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2079 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2080 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 [10]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 [10]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 [10]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0 [10]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<10> )
  );
  LUT6 #(
    .INIT ( 64'hFD75B931EC64A820 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/Mmux_rd_addr[1]_word2[17]_wide_mux_9_OUT181  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2079 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2080 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 [9]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 [9]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 [9]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0 [9]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<9> )
  );
  LUT6 #(
    .INIT ( 64'hFD75B931EC64A820 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/Mmux_rd_addr[1]_word2[17]_wide_mux_9_OUT171  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2079 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2080 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 [8]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 [8]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 [8]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0 [8]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<8> )
  );
  LUT6 #(
    .INIT ( 64'hFD75B931EC64A820 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/Mmux_rd_addr[1]_word2[17]_wide_mux_9_OUT161  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2079 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2080 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 [7]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 [7]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 [7]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0 [7]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<7> )
  );
  LUT6 #(
    .INIT ( 64'hFD75B931EC64A820 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/Mmux_rd_addr[1]_word2[17]_wide_mux_9_OUT151  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2079 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2080 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 [6]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 [6]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 [6]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0 [6]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<6> )
  );
  LUT6 #(
    .INIT ( 64'hFD75B931EC64A820 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/Mmux_rd_addr[1]_word2[17]_wide_mux_9_OUT141  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2079 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2080 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 [5]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 [5]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 [5]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0 [5]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<5> )
  );
  LUT6 #(
    .INIT ( 64'hFD75B931EC64A820 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/Mmux_rd_addr[1]_word2[17]_wide_mux_9_OUT131  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2079 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2080 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 [4]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 [4]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 [4]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0 [4]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<4> )
  );
  LUT6 #(
    .INIT ( 64'hFD75B931EC64A820 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/Mmux_rd_addr[1]_word2[17]_wide_mux_9_OUT121  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2079 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2080 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 [3]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0 [3]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<3> )
  );
  LUT6 #(
    .INIT ( 64'hFD75B931EC64A820 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/Mmux_rd_addr[1]_word2[17]_wide_mux_9_OUT111  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2079 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2080 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 [2]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0 [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<2> )
  );
  LUT6 #(
    .INIT ( 64'hFD75B931EC64A820 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/Mmux_rd_addr[1]_word2[17]_wide_mux_9_OUT101  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2079 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2080 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0 [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<1> )
  );
  LUT6 #(
    .INIT ( 64'hFD75B931EC64A820 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/Mmux_rd_addr[1]_word2[17]_wide_mux_9_OUT11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2079 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2080 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word1 [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word2 [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word3 [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/word0 [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/rd_addr[1]_word2[17]_wide_mux_9_OUT<0> )
  );
  LUT2 #(
    .INIT ( 4'h1 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0037<1>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0037 )
  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0043<1>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0043 )
  );
  LUT2 #(
    .INIT ( 4'h8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0045<1>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0045 )
  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0040<1>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/_n0040 )
  );
  LUT6 #(
    .INIT ( 64'h6AAAAAAAAAAAAAAA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_ber_count_xor<5>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [5]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [3]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [4]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [5])
  );
  LUT5 #(
    .INIT ( 32'h6AAAAAAA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_ber_count_xor<4>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [4]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [3]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [4])
  );
  LUT4 #(
    .INIT ( 16'h6AAA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_ber_count_xor<3>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [3])
  );
  LUT3 #(
    .INIT ( 8'h6A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_ber_count_xor<2>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [2])
  );
  LUT2 #(
    .INIT ( 4'h6 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_ber_count_xor<1>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [1])
  );
  LUT4 #(
    .INIT ( 16'h6AAA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Result<3>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Result [3])
  );
  LUT5 #(
    .INIT ( 32'h6AAAAAAA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Result<4>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [4]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Result [4])
  );
  LUT6 #(
    .INIT ( 64'h6AAAAAAAAAAAAAAA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Result<5>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [5]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [4]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Result [5])
  );
  LUT3 #(
    .INIT ( 8'h20 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/_n00792  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/read_enable_2252 ),
    .I1(txreset322),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/_n00791_2243 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/_n0079 )
  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Mcount_txsequence_int_val1  (
    .I0(txreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/_n00791_2243 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Mcount_txsequence_int_val )
  );
  LUT3 #(
    .INIT ( 8'h6A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Mcount_txsequence_int_xor<2>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Result [2])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Mmux_tx_34_gt<2>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [34]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [2])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Mmux_tx_34_gt<3>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [35]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [3])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Mmux_tx_34_gt<4>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [4]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [36]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [4])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Mmux_tx_34_gt<5>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [37]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [5])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Mmux_tx_34_gt<6>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [6]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [38]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [6])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Mmux_tx_34_gt<7>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [7]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [39]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [7])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Mmux_tx_34_gt<8>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [8]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [40]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [8])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Mmux_tx_34_gt<9>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [9]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [41]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [9])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Mmux_tx_34_gt<10>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [10]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [42]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [10])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Mmux_tx_34_gt<11>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [11]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [43]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [11])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Mmux_tx_34_gt<12>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [12]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [44]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [12])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Mmux_tx_34_gt<13>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [13]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [45]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [13])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Mmux_tx_34_gt<14>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [14]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [46]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [14])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Mmux_tx_34_gt<16>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [16]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [48]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [16])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Mmux_tx_34_gt<17>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [17]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [49]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [17])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Mmux_tx_34_gt<15>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [15]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [47]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [15])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Mmux_tx_34_gt<18>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [18]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [50]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [18])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Mmux_tx_34_gt<19>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [19]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [51]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [19])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Mmux_tx_34_gt<20>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [20]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [52]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [20])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Mmux_tx_34_gt<21>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [21]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [53]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [21])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Mmux_tx_34_gt<22>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [22]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [54]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [22])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Mmux_tx_34_gt<23>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [23]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [55]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [23])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Mmux_tx_34_gt<24>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [24]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [56]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [24])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Mmux_tx_34_gt<25>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [25]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [57]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [25])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Mmux_tx_34_gt<26>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [26]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [58]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [26])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Mmux_tx_34_gt<27>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [27]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [59]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [27])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Mmux_tx_34_gt<28>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [28]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [60]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [28])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Mmux_tx_34_gt<29>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [29]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [61]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [29])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Mmux_tx_34_gt<30>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [30]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [62]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [30])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Mmux_tx_34_gt<31>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [31]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [63]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [31])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Mmux_tx_34_gt<33>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [33]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [65]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [33])
  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Mmux_tx_34_gt<32>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [32]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/rd_data [64]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_34_gt [32])
  );
  LUT2 #(
    .INIT ( 4'h6 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Mcount_txsequence_int_xor<1>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Result [1])
  );
  LUT4 #(
    .INIT ( 16'h6AAA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Mcount_wr_addr_xor<3>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Result [3])
  );
  LUT3 #(
    .INIT ( 8'h6A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Mcount_wr_addr_xor<2>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Result [2])
  );
  LUT4 #(
    .INIT ( 16'h6AAA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Mcount_rd_addr_xor<3>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Result<3>1 )
  );
  LUT3 #(
    .INIT ( 8'h6A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Mcount_rd_addr_xor<2>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Result<2>1 )
  );
  LUT4 #(
    .INIT ( 16'hA965 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/fcomp<3>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_lastgray_wrclk [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/full_int_838 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_gray [3]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/fcomp [3])
  );
  LUT4 #(
    .INIT ( 16'hA965 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/fcomp<2>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_lastgray_wrclk [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/full_int_838 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_gray [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/fcomp [2])
  );
  LUT4 #(
    .INIT ( 16'hA965 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/fcomp<1>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_lastgray_wrclk [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/full_int_838 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_gray [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/fcomp [1])
  );
  LUT4 #(
    .INIT ( 16'hA965 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/fcomp<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_lastgray_wrclk [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/full_int_838 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_gray [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/fcomp [0])
  );
  LUT4 #(
    .INIT ( 16'hA965 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ecomp<3>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_gray_rdclk [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/empty_int_2366 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_gray [3]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ecomp [3])
  );
  LUT4 #(
    .INIT ( 16'hA965 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ecomp<2>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_gray_rdclk [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/empty_int_2366 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_gray [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ecomp [2])
  );
  LUT4 #(
    .INIT ( 16'hA965 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ecomp<1>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_gray_rdclk [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/empty_int_2366 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_gray [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ecomp [1])
  );
  LUT4 #(
    .INIT ( 16'hA965 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ecomp<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_gray_rdclk [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/empty_int_2366 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_gray [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ecomp [0])
  );
  LUT2 #(
    .INIT ( 4'h6 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Result<1>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Result<1>1_2327 )
  );
  LUT2 #(
    .INIT ( 4'h6 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Result<1>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Result [1])
  );
  LUT2 #(
    .INIT ( 4'h6 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Mxor_wr_addr[3]_wr_addr[2]_XOR_5_o_xo<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3] ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[3]_wr_addr[2]_XOR_5_o )
  );
  LUT2 #(
    .INIT ( 4'h6 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Mxor_wr_addr[2]_wr_addr[1]_XOR_6_o_xo<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_nextgray [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2] ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[2]_wr_addr[1]_XOR_6_o )
  );
  LUT2 #(
    .INIT ( 4'h6 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Mxor_rd_addr[3]_rd_addr[2]_XOR_2_o_xo<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3] ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[3]_rd_addr[2]_XOR_2_o )
  );
  LUT2 #(
    .INIT ( 4'h6 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Mxor_rd_addr[2]_rd_addr[1]_XOR_3_o_xo<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_nextgray [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2] ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[2]_rd_addr[1]_XOR_3_o )
  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Mmux_rd_truegray[3]_GND_15_o_mux_65_OUT11  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_truegray [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_truegray[3]_GND_15_o_mux_65_OUT<0> )
  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Mmux_rd_truegray[3]_GND_15_o_mux_65_OUT21  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_truegray [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_truegray[3]_GND_15_o_mux_65_OUT<1> )
  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Mmux_rd_truegray[3]_GND_15_o_mux_65_OUT31  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_truegray [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_truegray[3]_GND_15_o_mux_65_OUT<2> )
  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Mmux_rd_truegray[3]_GND_15_o_mux_65_OUT41  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_truegray [3]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_truegray[3]_GND_15_o_mux_65_OUT<3> )
  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Mmux_rag_writesync0[3]_GND_15_o_mux_66_OUT11  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rag_writesync0 [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rag_writesync0[3]_GND_15_o_mux_66_OUT<0> )
  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Mmux_rag_writesync0[3]_GND_15_o_mux_66_OUT21  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rag_writesync0 [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rag_writesync0[3]_GND_15_o_mux_66_OUT<1> )
  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Mmux_rag_writesync0[3]_GND_15_o_mux_66_OUT31  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rag_writesync0 [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rag_writesync0[3]_GND_15_o_mux_66_OUT<2> )
  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Mmux_rag_writesync0[3]_GND_15_o_mux_66_OUT41  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rag_writesync0 [3]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rag_writesync0[3]_GND_15_o_mux_66_OUT<3> )
  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/empty_int_2366 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/read_enable_2252 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_rd_en )
  );
  LUT2 #(
    .INIT ( 4'h1 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/can_insert<3>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/status [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/status [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/can_insert )
  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/can_insert_wra_comb1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/can_insert_wra ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/can_insert_wra2 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/can_insert_wra_comb )
  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1112  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [32]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [0]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<0> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1101  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [50]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [18]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<18> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1113  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [51]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [19]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<19> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1121  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [33]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<1> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1131  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [52]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [20]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<20> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1141  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [53]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [21]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<21> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1151  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [54]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [22]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<22> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1161  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [55]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [23]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<23> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1181  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [57]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [25]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<25> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1191  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [58]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [26]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<26> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1210  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [42]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [10]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<10> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1201  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [59]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [27]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<27> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1211  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [60]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [28]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<28> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1221  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [61]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [29]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<29> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1241  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [62]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [30]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<30> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1251  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [63]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [31]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<31> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1261  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [0]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [32]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<32> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1271  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [1]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [33]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<33> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1310  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [43]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [11]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<11> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1311  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [5]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [37]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<37> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1321  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [6]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [38]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<38> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1351  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [8]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [40]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<40> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1361  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [9]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [41]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<41> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1371  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [10]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [42]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<42> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1381  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [11]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [43]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<43> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1391  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [12]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [44]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<44> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1410  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [44]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [12]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<12> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1401  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [13]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [45]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<45> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1411  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [14]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [46]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<46> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1421  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [15]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [47]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<47> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1431  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [16]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [48]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<48> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1441  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [17]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [49]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<49> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1461  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [18]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [50]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<50> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1471  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [19]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [51]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<51> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1481  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [20]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [52]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<52> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1491  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [21]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [53]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<53> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1510  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [45]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [13]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<13> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1501  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [22]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [54]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<54> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1511  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [23]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [55]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<55> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1531  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [25]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [57]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<57> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1541  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [26]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [58]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<58> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1551  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [27]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [59]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<59> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1561  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [37]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [5]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<5> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1571  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [28]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [60]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<60> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1581  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [29]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [61]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<61> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1591  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [30]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [62]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<62> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT165  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [46]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [14]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<14> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1601  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [31]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [63]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<63> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1611  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [38]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [6]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<6> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1631  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [40]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [8]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<8> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1641  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [41]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [9]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<9> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT171  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [47]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [15]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<15> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT181  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [48]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [16]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<16> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT191  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [49]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [17]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<17> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT21  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_delay [5]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out[7]_GND_34_o_mux_32_OUT<1> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT31  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_delay [6]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out[7]_GND_34_o_mux_32_OUT<2> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT41  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_delay [7]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out[7]_GND_34_o_mux_32_OUT<3> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT61  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe [1]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe [5]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out[7]_GND_34_o_mux_32_OUT<5> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT71  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe [2]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe [6]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out[7]_GND_34_o_mux_32_OUT<6> )

  );
  LUT5 #(
    .INIT ( 32'h44454440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT81  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe [3]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe [7]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out[7]_GND_34_o_mux_32_OUT<7> )

  );
  LUT6 #(
    .INIT ( 64'h66666EEE6EEE6EEE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT11101  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3_2877 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd2_2878 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_seq [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_was_seq_2765 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_idle [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_was_idle_2766 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )

  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_ctrl_delay[7]_GND_34_o_mux_19_OUT11  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe [4]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_delay[7]_GND_34_o_mux_19_OUT<0> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_ctrl_delay[7]_GND_34_o_mux_19_OUT21  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe [5]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_delay[7]_GND_34_o_mux_19_OUT<1> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_ctrl_delay[7]_GND_34_o_mux_19_OUT31  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe [6]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_delay[7]_GND_34_o_mux_19_OUT<2> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_ctrl_delay[7]_GND_34_o_mux_19_OUT41  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe [7]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_delay[7]_GND_34_o_mux_19_OUT<3> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_delay[63]_GND_34_o_mux_18_OUT110  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [32]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<0> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_delay[63]_GND_34_o_mux_18_OUT210  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [42]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<10> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_delay[63]_GND_34_o_mux_18_OUT33  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [43]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<11> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_delay[63]_GND_34_o_mux_18_OUT41  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [44]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<12> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_delay[63]_GND_34_o_mux_18_OUT51  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [45]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<13> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_delay[63]_GND_34_o_mux_18_OUT61  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [46]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<14> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_delay[63]_GND_34_o_mux_18_OUT71  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [47]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<15> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_delay[63]_GND_34_o_mux_18_OUT81  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [48]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<16> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_delay[63]_GND_34_o_mux_18_OUT91  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [49]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<17> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_delay[63]_GND_34_o_mux_18_OUT101  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [50]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<18> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_delay[63]_GND_34_o_mux_18_OUT111  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [51]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<19> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_delay[63]_GND_34_o_mux_18_OUT121  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [33]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<1> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_delay[63]_GND_34_o_mux_18_OUT131  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [52]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<20> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_delay[63]_GND_34_o_mux_18_OUT141  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [53]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<21> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_delay[63]_GND_34_o_mux_18_OUT151  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [54]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<22> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_delay[63]_GND_34_o_mux_18_OUT161  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [55]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<23> )

  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_delay[63]_GND_34_o_mux_18_OUT171  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [56]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<24> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_delay[63]_GND_34_o_mux_18_OUT181  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [57]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<25> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_delay[63]_GND_34_o_mux_18_OUT191  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [58]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<26> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_delay[63]_GND_34_o_mux_18_OUT201  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [59]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<27> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_delay[63]_GND_34_o_mux_18_OUT211  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [60]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<28> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_delay[63]_GND_34_o_mux_18_OUT221  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [61]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<29> )

  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_delay[63]_GND_34_o_mux_18_OUT231  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [34]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<2> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_delay[63]_GND_34_o_mux_18_OUT241  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [62]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<30> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_delay[63]_GND_34_o_mux_18_OUT251  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [63]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<31> )

  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_delay[63]_GND_34_o_mux_18_OUT261  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [35]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<3> )

  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_delay[63]_GND_34_o_mux_18_OUT271  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [36]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<4> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_delay[63]_GND_34_o_mux_18_OUT281  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [37]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<5> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_delay[63]_GND_34_o_mux_18_OUT291  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [38]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<6> )

  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_delay[63]_GND_34_o_mux_18_OUT301  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [39]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<7> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_delay[63]_GND_34_o_mux_18_OUT311  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [40]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<8> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_delay[63]_GND_34_o_mux_18_OUT321  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [41]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay[63]_GND_34_o_mux_18_OUT<9> )

  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_ctrl_pipe[7]_GND_34_o_mux_7_OUT11  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl [0]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe[7]_GND_34_o_mux_7_OUT<0> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_ctrl_pipe[7]_GND_34_o_mux_7_OUT21  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe[7]_GND_34_o_mux_7_OUT<1> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_ctrl_pipe[7]_GND_34_o_mux_7_OUT31  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe[7]_GND_34_o_mux_7_OUT<2> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_ctrl_pipe[7]_GND_34_o_mux_7_OUT41  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe[7]_GND_34_o_mux_7_OUT<3> )

  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_ctrl_pipe[7]_GND_34_o_mux_7_OUT51  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl [4]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe[7]_GND_34_o_mux_7_OUT<4> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_ctrl_pipe[7]_GND_34_o_mux_7_OUT61  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl [5]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe[7]_GND_34_o_mux_7_OUT<5> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_ctrl_pipe[7]_GND_34_o_mux_7_OUT71  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl [6]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe[7]_GND_34_o_mux_7_OUT<6> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_ctrl_pipe[7]_GND_34_o_mux_7_OUT81  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl [7]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe[7]_GND_34_o_mux_7_OUT<7> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT110  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [0]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<0> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT210  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [10]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<10> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT310  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [11]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<11> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT410  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [12]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<12> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT510  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [13]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<13> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT65  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [14]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<14> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT71  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [15]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<15> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT81  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [16]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<16> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT91  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [17]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<17> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT101  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [18]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<18> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT111  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [19]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<19> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT121  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<1> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT131  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [20]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<20> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT141  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [21]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<21> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT151  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [22]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<22> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT161  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [23]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<23> )

  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT171  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [24]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<24> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT181  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [25]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<25> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT191  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [26]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<26> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT201  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [27]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<27> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT211  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [28]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<28> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT221  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [29]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<29> )

  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT231  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<2> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT241  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [30]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<30> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT251  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [31]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<31> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT261  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [32]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<32> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT271  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [33]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<33> )

  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT281  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [34]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<34> )

  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT291  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [35]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<35> )

  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT301  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [36]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<36> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT311  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [37]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<37> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT321  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [38]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<38> )

  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT331  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [39]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<39> )

  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT341  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<3> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT351  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [40]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<40> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT361  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [41]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<41> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT371  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [42]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<42> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT381  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [43]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<43> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT391  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [44]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<44> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT401  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [45]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<45> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT411  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [46]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<46> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT421  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [47]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<47> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT431  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [48]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<48> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT441  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [49]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<49> )

  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT451  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [4]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<4> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT461  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [50]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<50> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT471  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [51]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<51> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT481  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [52]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<52> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT491  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [53]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<53> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT501  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [54]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<54> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT511  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [55]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<55> )

  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT521  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [56]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<56> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT531  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [57]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<57> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT541  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [58]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<58> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT551  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [59]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<59> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT561  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [5]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<5> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT571  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [60]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<60> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT581  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [61]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<61> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT591  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [62]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<62> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT601  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [63]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<63> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT611  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [6]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<6> )

  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT621  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [7]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<7> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT631  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [8]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<8> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_data_pipe[63]_GND_34_o_mux_6_OUT641  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [9]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe[63]_GND_34_o_mux_6_OUT<9> )

  );
  LUT4 #(
    .INIT ( 16'h0008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i0/comp<0><3>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i0/comp [0])
  );
  LUT4 #(
    .INIT ( 16'h0008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i0/comp<1><7>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [7]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [4]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [6]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [5]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i0/comp [1])
  );
  LUT4 #(
    .INIT ( 16'h0002 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i0/comp<2><3>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i0/comp [2])
  );
  LUT4 #(
    .INIT ( 16'h0008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i1/comp<0><3>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [35]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [34]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [33]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [32]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i1/comp [0])
  );
  LUT4 #(
    .INIT ( 16'h0008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i1/comp<1><7>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [39]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [36]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [38]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [37]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i1/comp [1])
  );
  LUT4 #(
    .INIT ( 16'h0002 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i1/comp<2><3>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl [4]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl [7]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl [6]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl [5]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/seq_detect_i1/comp [2])
  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv1  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/_n0114_inv )
  );
  LUT4 #(
    .INIT ( 16'h0001 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/comp<7><31>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [63]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [62]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [61]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [60]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/comp [7])
  );
  LUT4 #(
    .INIT ( 16'h0001 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/comp<5><23>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [55]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [54]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [53]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [52]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/comp [5])
  );
  LUT4 #(
    .INIT ( 16'h0001 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/comp<3><15>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [47]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [46]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [45]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [44]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/comp [3])
  );
  LUT4 #(
    .INIT ( 16'h0001 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/comp<1><7>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [39]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [38]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [37]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [36]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/comp [1])
  );
  LUT4 #(
    .INIT ( 16'h8000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/comp<8><3>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl [7]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl [6]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl [5]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl [4]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/comp [8])
  );
  LUT4 #(
    .INIT ( 16'h0800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/comp<6><27>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [57]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [58]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [59]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [56]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/comp [6])
  );
  LUT4 #(
    .INIT ( 16'h0800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/comp<4><19>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [49]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [50]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [51]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [48]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/comp [4])
  );
  LUT4 #(
    .INIT ( 16'h0800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/comp<2><11>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [41]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [42]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [43]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [40]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/comp [2])
  );
  LUT4 #(
    .INIT ( 16'h0800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/comp<0><3>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [33]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [34]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [35]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [32]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i1/comp [0])
  );
  LUT4 #(
    .INIT ( 16'h0001 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/comp<7><31>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [31]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [30]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [29]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [28]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/comp [7])
  );
  LUT4 #(
    .INIT ( 16'h0001 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/comp<5><23>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [23]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [22]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [21]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [20]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/comp [5])
  );
  LUT4 #(
    .INIT ( 16'h0001 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/comp<3><15>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [15]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [14]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [13]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [12]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/comp [3])
  );
  LUT4 #(
    .INIT ( 16'h0001 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/comp<1><7>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [7]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [6]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [5]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [4]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/comp [1])
  );
  LUT4 #(
    .INIT ( 16'h8000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/comp<8><3>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/comp [8])
  );
  LUT4 #(
    .INIT ( 16'h0800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/comp<6><27>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [25]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [26]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [27]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [24]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/comp [6])
  );
  LUT4 #(
    .INIT ( 16'h0800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/comp<4><19>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [17]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [18]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [19]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [16]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/comp [4])
  );
  LUT4 #(
    .INIT ( 16'h0800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/comp<2><11>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [9]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [10]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [11]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [8]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/comp [2])
  );
  LUT4 #(
    .INIT ( 16'h0800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/comp<0><3>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/idle_detect_i0/comp [0])
  );
  LUT4 #(
    .INIT ( 16'h6AAA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Mcount_wr_addr_xor<3>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Result [3])
  );
  LUT3 #(
    .INIT ( 8'h6A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Mcount_wr_addr_xor<2>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Result [2])
  );
  LUT4 #(
    .INIT ( 16'h6AAA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Mcount_rd_addr_xor<3>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Result<3>1 )
  );
  LUT3 #(
    .INIT ( 8'h6A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Mcount_rd_addr_xor<2>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Result<2>1 )
  );
  LUT4 #(
    .INIT ( 16'hA965 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/fcomp<3>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray_wrclk [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/full_int_3072 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_nextgray [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray [3]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/fcomp [3])
  );
  LUT4 #(
    .INIT ( 16'hA965 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/fcomp<2>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray_wrclk [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/full_int_3072 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_nextgray [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/fcomp [2])
  );
  LUT4 #(
    .INIT ( 16'hA965 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/fcomp<1>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray_wrclk [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/full_int_3072 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_nextgray [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/fcomp [1])
  );
  LUT4 #(
    .INIT ( 16'hA965 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/fcomp<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray_wrclk [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/full_int_3072 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/fcomp [0])
  );
  LUT4 #(
    .INIT ( 16'hA965 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ecomp<3>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray_rdclk [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_nextgray [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_gray [3]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ecomp [3])
  );
  LUT4 #(
    .INIT ( 16'hA965 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ecomp<2>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray_rdclk [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_nextgray [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_gray [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ecomp [2])
  );
  LUT4 #(
    .INIT ( 16'hA965 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ecomp<1>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray_rdclk [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_nextgray [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_gray [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ecomp [1])
  );
  LUT4 #(
    .INIT ( 16'hA965 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ecomp<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray_rdclk [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_gray [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ecomp [0])
  );
  LUT3 #(
    .INIT ( 8'h14 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Mmux_wr_nextgray[3]_PWR_39_o_mux_44_OUT21  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_nextgray[3]_PWR_39_o_mux_44_OUT<1> )

  );
  LUT3 #(
    .INIT ( 8'h14 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Mmux_wr_nextgray[3]_PWR_39_o_mux_44_OUT31  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_nextgray[3]_PWR_39_o_mux_44_OUT<2> )

  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Mmux_rd_nextgray[3]_PWR_39_o_mux_19_OUT41  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_nextgray[3]_PWR_39_o_mux_19_OUT<3> )

  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Mmux_wr_nextgray[3]_PWR_39_o_mux_44_OUT41  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_nextgray[3]_PWR_39_o_mux_44_OUT<3> )

  );
  LUT2 #(
    .INIT ( 4'h6 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Result<1>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Result<1>1_2989 )
  );
  LUT2 #(
    .INIT ( 4'h6 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Result<1>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Result [1])
  );
  LUT2 #(
    .INIT ( 4'h6 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Mxor_ra_writesync<2>_xo<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync [3]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ra_writesync [2])
  );
  LUT2 #(
    .INIT ( 4'h6 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Mxor_rd_addr[3]_rd_addr[2]_XOR_509_o_xo<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr[3]_rd_addr[2]_XOR_509_o )

  );
  LUT2 #(
    .INIT ( 4'h6 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Mxor_rd_addr[2]_rd_addr[1]_XOR_510_o_xo<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr[2]_rd_addr[1]_XOR_510_o )

  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Mmux_rd_lastgray[3]_PWR_39_o_mux_31_OUT11  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_gray [0]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray[3]_PWR_39_o_mux_31_OUT<0> )

  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Mmux_rd_lastgray[3]_PWR_39_o_mux_31_OUT21  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_gray [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray[3]_PWR_39_o_mux_31_OUT<1> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Mmux_rd_lastgray[3]_PWR_39_o_mux_31_OUT31  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_gray [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray[3]_PWR_39_o_mux_31_OUT<2> )

  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Mmux_rd_lastgray[3]_PWR_39_o_mux_31_OUT41  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_gray [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_lastgray[3]_PWR_39_o_mux_31_OUT<3> )

  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Mmux_rd_gray[3]_PWR_39_o_mux_25_OUT11  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_gray[3]_PWR_39_o_mux_25_OUT<0> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Mmux_rd_gray[3]_PWR_39_o_mux_25_OUT21  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_nextgray [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_gray[3]_PWR_39_o_mux_25_OUT<1> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Mmux_rd_gray[3]_PWR_39_o_mux_25_OUT31  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_nextgray [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_gray[3]_PWR_39_o_mux_25_OUT<2> )

  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Mmux_rd_gray[3]_PWR_39_o_mux_25_OUT41  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_nextgray [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_gray[3]_PWR_39_o_mux_25_OUT<3> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Mmux_rag_writesync0[3]_GND_37_o_mux_66_OUT11  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync0 [0]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync0[3]_GND_37_o_mux_66_OUT<0> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Mmux_rag_writesync0[3]_GND_37_o_mux_66_OUT21  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync0 [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync0[3]_GND_37_o_mux_66_OUT<1> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Mmux_rag_writesync0[3]_GND_37_o_mux_66_OUT31  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync0 [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync0[3]_GND_37_o_mux_66_OUT<2> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Mmux_rag_writesync0[3]_GND_37_o_mux_66_OUT41  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync0 [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync0[3]_GND_37_o_mux_66_OUT<3> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Mmux_rd_truegray[3]_GND_37_o_mux_65_OUT11  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_truegray [0]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_truegray[3]_GND_37_o_mux_65_OUT<0> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Mmux_rd_truegray[3]_GND_37_o_mux_65_OUT21  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_truegray [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_truegray[3]_GND_37_o_mux_65_OUT<1> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Mmux_rd_truegray[3]_GND_37_o_mux_65_OUT31  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_truegray [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_truegray[3]_GND_37_o_mux_65_OUT<2> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Mmux_rd_truegray[3]_GND_37_o_mux_65_OUT41  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_truegray [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_truegray[3]_GND_37_o_mux_65_OUT<3> )

  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Mmux_wr_gray[3]_PWR_39_o_mux_50_OUT11  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray[3]_PWR_39_o_mux_50_OUT<0> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Mmux_wr_gray[3]_PWR_39_o_mux_50_OUT21  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_nextgray [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray[3]_PWR_39_o_mux_50_OUT<1> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Mmux_wr_gray[3]_PWR_39_o_mux_50_OUT31  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_nextgray [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray[3]_PWR_39_o_mux_50_OUT<2> )

  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Mmux_wr_gray[3]_PWR_39_o_mux_50_OUT41  (
    .I0(rxreset322),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_nextgray [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_gray[3]_PWR_39_o_mux_50_OUT<3> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_en ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_rd_en )
  );
  LUT5 #(
    .INIT ( 32'h44404044 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/full_int_3072 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3_2877 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd2_2878 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ram_wr_en )
  );
  LUT3 #(
    .INIT ( 8'h69 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Msub_wr_addr_pipe[3]_ra_writesync[3]_sub_81_OUT_xor<3>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync [3]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Msub_wr_addr_pipe[3]_ra_writesync[3]_sub_81_OUT_cy<2> )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe[3]_ra_writesync[3]_sub_81_OUT<3> )

  );
  LUT4 #(
    .INIT ( 16'h0800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/comp<0><3>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [33]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [34]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [35]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [32]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/comp [0])
  );
  LUT4 #(
    .INIT ( 16'h0800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/comp<2><11>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [41]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [42]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [43]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [40]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/comp [2])
  );
  LUT4 #(
    .INIT ( 16'h0800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/comp<4><19>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [49]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [50]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [51]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [48]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/comp [4])
  );
  LUT4 #(
    .INIT ( 16'h0800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/comp<6><27>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [57]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [58]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [59]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [56]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/comp [6])
  );
  LUT4 #(
    .INIT ( 16'h8000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/comp<8><3>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [71]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [70]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [69]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [68]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/comp [8])
  );
  LUT4 #(
    .INIT ( 16'h0001 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/comp<1><7>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [39]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [38]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [37]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [36]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/comp [1])
  );
  LUT4 #(
    .INIT ( 16'h0001 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/comp<3><15>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [47]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [46]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [45]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [44]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/comp [3])
  );
  LUT4 #(
    .INIT ( 16'h0001 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/comp<5><23>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [55]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [54]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [53]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [52]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/comp [5])
  );
  LUT4 #(
    .INIT ( 16'h0001 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/comp<7><31>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [63]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [62]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [61]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [60]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i1/comp [7])
  );
  LUT4 #(
    .INIT ( 16'h0800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/comp<0><3>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/comp [0])
  );
  LUT4 #(
    .INIT ( 16'h0800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/comp<2><11>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [9]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [10]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [11]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [8]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/comp [2])
  );
  LUT4 #(
    .INIT ( 16'h0800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/comp<4><19>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [17]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [18]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [19]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [16]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/comp [4])
  );
  LUT4 #(
    .INIT ( 16'h0800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/comp<6><27>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [25]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [26]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [27]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [24]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/comp [6])
  );
  LUT4 #(
    .INIT ( 16'h8000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/comp<8><3>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [67]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [66]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [65]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [64]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/comp [8])
  );
  LUT4 #(
    .INIT ( 16'h0001 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/comp<1><7>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [7]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [6]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [5]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [4]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/comp [1])
  );
  LUT4 #(
    .INIT ( 16'h0001 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/comp<3><15>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [15]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [14]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [13]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [12]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/comp [3])
  );
  LUT4 #(
    .INIT ( 16'h0001 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/comp<5><23>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [23]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [22]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [21]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [20]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/comp [5])
  );
  LUT4 #(
    .INIT ( 16'h0001 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/comp<7><31>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [31]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [30]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [29]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [28]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/idle_detect_i0/comp [7])
  );
  LUT6 #(
    .INIT ( 64'hAAAA222AAAAAEEEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd3-In1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd3_3332 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/can_insert_rd ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd2_3333 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd1_3334 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd3-In )
  );
  LUT3 #(
    .INIT ( 8'h54 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_twist11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/local_fault_3335 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd3_3332 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd2_3333 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFFF4540 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1171  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [56]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [24]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<24> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFFF4540 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1521  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [24]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [56]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<56> )

  );
  LUT4 #(
    .INIT ( 16'h1014 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_jam_idle[0]_PWR_41_o_equal_16_o11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/local_fault_3335 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd3_3332 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd1_3334 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd2_3333 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o )

  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFF55544454 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1291  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [35]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [3]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<35> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFF55544454 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1301  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [36]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [4]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<36> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFF55544454 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1331  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [39]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [7]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<39> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFF55544454 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1341  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [35]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<3> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFF55544454 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1451  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [4]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [36]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<4> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFF55544454 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1621  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [7]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [39]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<7> )

  );
  LUT6 #(
    .INIT ( 64'h5555555510111000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT111  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [32]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [0]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<0> )

  );
  LUT6 #(
    .INIT ( 64'h5555555510111000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT181  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [48]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [16]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<16> )

  );
  LUT6 #(
    .INIT ( 64'h5555555510111000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1261  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [32]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<32> )

  );
  LUT6 #(
    .INIT ( 64'h5555555510111000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1351  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [8]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [40]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<40> )

  );
  LUT6 #(
    .INIT ( 64'h5555555510111000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1431  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [16]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [48]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<48> )

  );
  LUT6 #(
    .INIT ( 64'h5555555510111000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1631  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [40]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [8]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<8> )

  );
  LUT6 #(
    .INIT ( 64'h0101010101000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_jam_idle[1]_PWR_41_o_equal_19_o11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/local_fault_3335 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd3_3332 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd1_3334 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/can_insert_rd ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd2_3333 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o )

  );
  LUT6 #(
    .INIT ( 64'h5555155544445555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_rd_en11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/local_fault_3335 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd3_3332 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/can_insert_rd ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd2_3333 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd1_3334 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_en )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFFFFFD8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_delay [4]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [64]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o )
,
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_in[7]_GND_39_o_mux_22_OUT<0> )

  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_3_OUT11  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [68]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_in[7]_GND_39_o_mux_3_OUT<0> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_3_OUT21  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [69]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_in[7]_GND_39_o_mux_3_OUT<1> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_3_OUT31  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [70]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_in[7]_GND_39_o_mux_3_OUT<2> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_3_OUT41  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [71]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_in[7]_GND_39_o_mux_3_OUT<3> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_data_in[63]_GND_39_o_mux_2_OUT110  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [32]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<0> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_data_in[63]_GND_39_o_mux_2_OUT210  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [42]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<10> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_data_in[63]_GND_39_o_mux_2_OUT33  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [43]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<11> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_data_in[63]_GND_39_o_mux_2_OUT41  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [44]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<12> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_data_in[63]_GND_39_o_mux_2_OUT51  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [45]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<13> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_data_in[63]_GND_39_o_mux_2_OUT61  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [46]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<14> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_data_in[63]_GND_39_o_mux_2_OUT71  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [47]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<15> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_data_in[63]_GND_39_o_mux_2_OUT81  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [48]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<16> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_data_in[63]_GND_39_o_mux_2_OUT91  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [49]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<17> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_data_in[63]_GND_39_o_mux_2_OUT101  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [50]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<18> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_data_in[63]_GND_39_o_mux_2_OUT111  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [51]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<19> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_data_in[63]_GND_39_o_mux_2_OUT121  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [33]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<1> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_data_in[63]_GND_39_o_mux_2_OUT131  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [52]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<20> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_data_in[63]_GND_39_o_mux_2_OUT141  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [53]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<21> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_data_in[63]_GND_39_o_mux_2_OUT151  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [54]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<22> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_data_in[63]_GND_39_o_mux_2_OUT161  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [55]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<23> )

  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_data_in[63]_GND_39_o_mux_2_OUT171  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [56]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<24> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_data_in[63]_GND_39_o_mux_2_OUT181  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [57]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<25> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_data_in[63]_GND_39_o_mux_2_OUT191  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [58]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<26> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_data_in[63]_GND_39_o_mux_2_OUT201  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [59]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<27> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_data_in[63]_GND_39_o_mux_2_OUT211  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [60]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<28> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_data_in[63]_GND_39_o_mux_2_OUT221  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [61]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<29> )

  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_data_in[63]_GND_39_o_mux_2_OUT231  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [34]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<2> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_data_in[63]_GND_39_o_mux_2_OUT241  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [62]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<30> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_data_in[63]_GND_39_o_mux_2_OUT251  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [63]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<31> )

  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_data_in[63]_GND_39_o_mux_2_OUT261  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [35]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<3> )

  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_data_in[63]_GND_39_o_mux_2_OUT271  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [36]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<4> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_data_in[63]_GND_39_o_mux_2_OUT281  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [37]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<5> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_data_in[63]_GND_39_o_mux_2_OUT291  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [38]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<6> )

  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_data_in[63]_GND_39_o_mux_2_OUT301  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [39]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<7> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_data_in[63]_GND_39_o_mux_2_OUT311  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [40]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<8> )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_data_in[63]_GND_39_o_mux_2_OUT321  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [41]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_2_OUT<9> )

  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o1  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/local_fault_3335 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o )
  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxheadervalid_503 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxdatavalid_504 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o )
  );
  LUT2 #(
    .INIT ( 4'h8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxdatavalid_504 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxheadervalid_503 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_4_o )
  );
  LUT4 #(
    .INIT ( 16'hFFFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_sync_1_counter_sync_extra_OR_558_o1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/q_3397 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_sync_extra_3395 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/q_3396 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/q_3398 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_sync_1_counter_sync_extra_OR_558_o )
  );
  LUT2 #(
    .INIT ( 4'h6 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/Mxor_out_comb_xo<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/newedge_3380 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/newedge_reg_3381 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/out_comb )
  );
  LUT2 #(
    .INIT ( 4'h6 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/Mxor_out_comb_xo<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/newedge_3388 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/newedge_reg_3389 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/out_comb )
  );
  LUT2 #(
    .INIT ( 4'h6 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/Mxor_out_comb_xo<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/newedge_3384 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/newedge_reg_3385 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/out_comb )
  );
  LUT4 #(
    .INIT ( 16'hFFFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_sync_1_counter_sync_extra_OR_558_o1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/q_3417 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_sync_extra_3415 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/q_3416 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/q_3418 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_sync_1_counter_sync_extra_OR_558_o )
  );
  LUT2 #(
    .INIT ( 4'h6 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/Mxor_out_comb_xo<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/newedge_3400 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/newedge_reg_3401 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/out_comb )
  );
  LUT2 #(
    .INIT ( 4'h6 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/Mxor_out_comb_xo<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/newedge_3408 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/newedge_reg_3409 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/out_comb )
  );
  LUT2 #(
    .INIT ( 4'h6 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/Mxor_out_comb_xo<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/newedge_3404 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/newedge_reg_3405 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/out_comb )
  );
  LUT4 #(
    .INIT ( 16'hFFFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_sync_1_counter_sync_extra_OR_558_o1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/q_3437 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_sync_extra_3435 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/q_3436 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/q_3438 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_sync_1_counter_sync_extra_OR_558_o )
  );
  LUT2 #(
    .INIT ( 4'h6 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/Mxor_out_comb_xo<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/newedge_3420 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/newedge_reg_3421 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/out_comb )
  );
  LUT2 #(
    .INIT ( 4'h6 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/Mxor_out_comb_xo<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/newedge_3428 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/newedge_reg_3429 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/out_comb )
  );
  LUT2 #(
    .INIT ( 4'h6 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/Mxor_out_comb_xo<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/newedge_3424 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/newedge_reg_3425 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/out_comb )
  );
  LUT5 #(
    .INIT ( 32'h00000008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_455_o<7>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [0]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o<7>1 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_455_o )
  );
  LUT5 #(
    .INIT ( 32'h00010000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_448_o<7>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [2]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o<7>1 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_448_o )
  );
  LUT5 #(
    .INIT ( 32'h00000001 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o<7>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [5]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [6]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o<7>1_3480 )

  );
  LUT6 #(
    .INIT ( 64'hFDFFECEE75776466 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_251_OUT21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [7]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [6]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2<4>_mmx_out1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [5]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2<5>_mmx_out ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2<5>_mmx_out2 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_251_OUT [1])
  );
  LUT6 #(
    .INIT ( 64'hFDFFECEE75776466 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_251_OUT31  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [6]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [7]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2<4>_mmx_out1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [5]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2<5>_mmx_out3 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2<5>_mmx_out2 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_251_OUT [2])
  );
  LUT6 #(
    .INIT ( 64'hFDFFECEE75776466 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_347_OUT21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [39]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [38]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2<36>_mmx_out1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [37]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2<37>_mmx_out ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2<37>_mmx_out2 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_347_OUT [1])
  );
  LUT6 #(
    .INIT ( 64'hFDFFECEE75776466 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_347_OUT31  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [38]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [39]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2<36>_mmx_out1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [37]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2<37>_mmx_out3 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2<37>_mmx_out2 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_347_OUT [2])
  );
  LUT4 #(
    .INIT ( 16'h8880 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT921  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_GND_22_o_equal_165_o ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[7]_tx_xgmii_data_reg1[7]_OR_155_o_3589 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_166_o ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_tx_xgmii_data_reg1[39]_OR_153_o_3588 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT92 )
  );
  LUT6 #(
    .INIT ( 64'h0080000080800080 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<7>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<1>11 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [58]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [60]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [62]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [61]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [63]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT [0])
  );
  LUT6 #(
    .INIT ( 64'h0080000080800080 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<7>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<1>11 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [50]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [52]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [54]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [53]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [55]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT [0])
  );
  LUT6 #(
    .INIT ( 64'h0080000080800080 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<7>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<1>11 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [42]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [44]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [46]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [45]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [47]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT [0])
  );
  LUT6 #(
    .INIT ( 64'h0080000080800080 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<7>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<1>11 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [26]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [28]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [30]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [29]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [31]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT [0])
  );
  LUT6 #(
    .INIT ( 64'h0080000080800080 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<7>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<1>11 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [18]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [20]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [22]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [21]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [23]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT [0])
  );
  LUT6 #(
    .INIT ( 64'h0080000080800080 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<7>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<1>11 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [10]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [12]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [14]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [13]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [15]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT [0])
  );
  LUT5 #(
    .INIT ( 32'hBB8AFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<4>31  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [59]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [56]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [60]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [57]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [58]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<4>3 )
  );
  LUT5 #(
    .INIT ( 32'hBB8AFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<4>31  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [51]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [48]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [52]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [49]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [50]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<4>3 )
  );
  LUT5 #(
    .INIT ( 32'hBB8AFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<4>31  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [43]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [40]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [44]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [41]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [42]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<4>3 )
  );
  LUT5 #(
    .INIT ( 32'hBB8AFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<4>31  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [27]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [24]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [28]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [25]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [26]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<4>3 )
  );
  LUT5 #(
    .INIT ( 32'hBB8AFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<4>31  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [19]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [16]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [20]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [17]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [18]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<4>3 )
  );
  LUT5 #(
    .INIT ( 32'hBB8AFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<4>31  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [11]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [8]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [12]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [9]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [10]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<4>3 )
  );
  LUT6 #(
    .INIT ( 64'h8000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_PWR_23_o_equal_185_o12  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[7]_tx_xgmii_data_reg1[7]_OR_155_o_3589 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[7]_reduce_and_188_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [7]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_PWR_23_o_equal_185_o2 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_PWR_23_o_equal_185_o3 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_PWR_23_o_equal_185_o_mmx_out )
  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[47]_PWR_23_o_equal_134_o2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[6] ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [41]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [40]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[7] ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [43]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[47]_tx_xgmii_data_reg1[47]_OR_94_o2 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[47]_PWR_23_o_equal_134_o_mmx_out )
  );
  LUT6 #(
    .INIT ( 64'hDFFFFFFFFFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[47]_PWR_23_o_equal_134_o11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[7] ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [41]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [40]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [43]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[47]_tx_xgmii_data_reg1[47]_OR_94_o2 )
,
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[6] ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[47]_PWR_23_o_equal_134_o_mmx_out1 )
  );
  LUT4 #(
    .INIT ( 16'h0008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o<7>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [7]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o<7>1_3480 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [4]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o )
  );
  LUT4 #(
    .INIT ( 16'h0002 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[2]_AND_57_o1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out231 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [0]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[2]_AND_57_o )
  );
  LUT5 #(
    .INIT ( 32'h00010000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n091511  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [7]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n09151_3483 )
  );
  LUT5 #(
    .INIT ( 32'h80000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[47]_tx_xgmii_data_reg1[47]_OR_94_o21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [42]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [44]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [47]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [46]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [45]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[47]_tx_xgmii_data_reg1[47]_OR_94_o2 )

  );
  LUT5 #(
    .INIT ( 32'h80000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[31]_tx_xgmii_data_reg1[31]_OR_80_o21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [26]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [28]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [30]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [31]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [29]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[31]_tx_xgmii_data_reg1[31]_OR_80_o2 )

  );
  LUT5 #(
    .INIT ( 32'hEAAAAAAA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT113221  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1711 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11321 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out231 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11322 )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFDBFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2<5>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [4]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [2]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [5]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2<5>_mmx_out )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFDBFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2<37>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [36]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [32]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [33]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [35]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [34]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [37]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2<37>_mmx_out )
  );
  LUT6 #(
    .INIT ( 64'hFDFFFFBFFFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2<5>31  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [5]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [4]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2<5>_mmx_out3 )
  );
  LUT6 #(
    .INIT ( 64'hFDFFFFBFFFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2<37>31  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [37]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [32]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [33]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [35]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [36]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [34]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2<37>_mmx_out3 )
  );
  LUT5 #(
    .INIT ( 32'hFFF8F8F8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<31>11  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o<7>1 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o<7>1 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [2]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_445_o<7>1 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<31>1 )
  );
  LUT5 #(
    .INIT ( 32'hFFFF4044 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [7]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o<7>1_3480 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [4]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>1 )
  );
  LUT3 #(
    .INIT ( 8'h10 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<31>21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [4]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [7]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o<7>1_3480 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<31>2 )
  );
  LUT3 #(
    .INIT ( 8'h10 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<1>4111  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [56]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [57]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [59]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<1>11 )
  );
  LUT3 #(
    .INIT ( 8'h10 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<1>4111  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [48]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [49]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [51]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<1>11 )
  );
  LUT3 #(
    .INIT ( 8'h10 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<1>4111  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [40]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [41]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [43]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<1>11 )
  );
  LUT3 #(
    .INIT ( 8'h10 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<1>4111  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [24]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [25]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [27]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<1>11 )
  );
  LUT3 #(
    .INIT ( 8'h10 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<1>4111  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [16]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [17]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [19]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<1>11 )
  );
  LUT3 #(
    .INIT ( 8'h10 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<1>4111  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [8]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [9]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [11]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<1>11 )
  );
  LUT5 #(
    .INIT ( 32'hFFFF0222 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1431  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[1]_AND_52_o )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out232 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out141 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[23]_PWR_23_o_equal_110_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT143_3443 )
  );
  LUT4 #(
    .INIT ( 16'hEA40 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1111121  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[4]_AND_64_o )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[5]_AND_66_o )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[55]_PWR_23_o_equal_142_o_mmx_out_3506 )
,
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[47]_PWR_23_o_equal_134_o_mmx_out1 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT111112 )
  );
  LUT5 #(
    .INIT ( 32'hFF9FFA9A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_347_OUT51  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [39]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [37]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [38]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2<36>_mmx_out1 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2<37>_mmx_out ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_347_OUT [4])
  );
  LUT5 #(
    .INIT ( 32'hFF9FFA9A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_251_OUT51  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [7]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [6]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2<4>_mmx_out1 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2<5>_mmx_out ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_251_OUT [4])
  );
  LUT5 #(
    .INIT ( 32'hFF9FFA9A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_347_OUT41  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [38]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [37]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [39]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2<36>_mmx_out1 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2<37>_mmx_out3 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_347_OUT [3])
  );
  LUT5 #(
    .INIT ( 32'hFF9FFA9A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_251_OUT41  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [6]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [7]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2<4>_mmx_out1 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2<5>_mmx_out3 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_251_OUT [3])
  );
  LUT4 #(
    .INIT ( 16'h0445 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_347_OUT11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2<36>_mmx_out1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [37]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [39]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [38]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_347_OUT [0])
  );
  LUT4 #(
    .INIT ( 16'h0445 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_251_OUT11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2<4>_mmx_out1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [7]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [6]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_251_OUT [0])
  );
  LUT5 #(
    .INIT ( 32'h55404040 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT641  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field [5]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d0 [5]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<7> )
  );
  LUT5 #(
    .INIT ( 32'h55404040 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT661  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field [7]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d0 [7]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<9> )
  );
  LUT6 #(
    .INIT ( 64'h5555555555404040 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT341  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field [1]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<60>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d0 [1]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>2 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<3> )
  );
  LUT6 #(
    .INIT ( 64'h5555555555404040 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT561  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field [3]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<60>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d0 [3]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>2 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<5> )
  );
  LUT5 #(
    .INIT ( 32'hAAAAA88A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n1230_inv1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [4]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2<36>_mmx_out1 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [38]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [39]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [37]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n1230_inv )
  );
  LUT5 #(
    .INIT ( 32'hAAAAA88A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n1043_inv1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2<4>_mmx_out1 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [6]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [7]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [5]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n1043_inv )
  );
  LUT3 #(
    .INIT ( 8'hFB ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT114111  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [5]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n09151_3483 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [4]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11411 )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFFFFFFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>111  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_448_o ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>111_3487 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_453_o<7>1 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>11 )
  );
  LUT3 #(
    .INIT ( 8'h01 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_PWR_23_o_equal_185_o31  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_PWR_23_o_equal_185_o3 )
  );
  LUT3 #(
    .INIT ( 8'h80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out2321  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out231 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out232 )
  );
  LUT3 #(
    .INIT ( 8'h20 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_453_o<7>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [7]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o<7>1_3480 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_453_o<7>1 )
  );
  LUT5 #(
    .INIT ( 32'h80000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_GND_22_o_equal_151_o2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [4]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_GND_22_o_equal_151_o1 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1141 )
  );
  LUT4 #(
    .INIT ( 16'h0002 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_GND_22_o_equal_151_o11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [6]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [7]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_GND_22_o_equal_151_o1 )
  );
  LUT5 #(
    .INIT ( 32'h00000008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o<7>2  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o<7>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [4]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [5]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [6]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [7]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o )
  );
  LUT4 #(
    .INIT ( 16'h8000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o<7>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o<7>1 )
  );
  LUT3 #(
    .INIT ( 8'h80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_445_o<7>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [2]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_445_o<7>1 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_445_o )
  );
  LUT3 #(
    .INIT ( 8'h80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_PWR_23_o_equal_185_o21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [4]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [6]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_PWR_23_o_equal_185_o2 )
  );
  LUT4 #(
    .INIT ( 16'h0002 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o<7>1  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o<7>1_3480 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [4]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [7]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o )
  );
  LUT4 #(
    .INIT ( 16'h0008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[1]_AND_52_o1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out231 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[1]_AND_52_o )
  );
  LUT4 #(
    .INIT ( 16'h8000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o<7>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [7]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [6]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [5]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [4]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o<7>1 )
  );
  LUT4 #(
    .INIT ( 16'h0800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[4]_AND_64_o1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [6]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [4]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n09151_3483 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[4]_AND_64_o )
  );
  LUT6 #(
    .INIT ( 64'hDFFFFFFFFFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2<37>21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [32]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [35]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [34]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [37]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [36]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [33]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2<37>_mmx_out2 )
  );
  LUT5 #(
    .INIT ( 32'hEFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2<36>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [32]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [33]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [35]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [34]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [36]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2<36>_mmx_out1 )
  );
  LUT6 #(
    .INIT ( 64'hDFFFFFFFFFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2<5>21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [5]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [4]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2<5>_mmx_out2 )
  );
  LUT5 #(
    .INIT ( 32'hEFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2<4>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [4]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2<4>_mmx_out1 )
  );
  LUT2 #(
    .INIT ( 4'h8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_126_o11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_126_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out1411 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_126_o_mmx_out1 )
  );
  LUT3 #(
    .INIT ( 8'hBF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_166_o21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_166_o ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[7]_tx_xgmii_data_reg1[7]_OR_155_o_3589 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_tx_xgmii_data_reg1[39]_OR_153_o_3588 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_166_o_mmx_out2 )
  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_t_type_reg[2]_GND_22_o_mux_458_OUT11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg[2]_GND_22_o_mux_458_OUT<0> )
  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_t_type_reg[2]_GND_22_o_mux_458_OUT21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg[2]_GND_22_o_mux_458_OUT<1> )
  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_t_type_reg[2]_GND_22_o_mux_458_OUT31  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg[2]_GND_22_o_mux_458_OUT<2> )
  );
  LUT5 #(
    .INIT ( 32'hFFF8F8F8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT231  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field [0]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>1 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d0 [0]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<2> )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFF8FFF8FFF8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT451  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field [2]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<60>1 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>2 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d0 [2]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<4> )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFF8FFF8FFF8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT631  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field [4]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<60>1 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>2 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d0 [4]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<6> )
  );
  LUT5 #(
    .INIT ( 32'hFFF8F8F8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT651  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field [6]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>1 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d0 [6]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<8> )
  );
  LUT4 #(
    .INIT ( 16'h8000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out211  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[3] ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[2] ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[1] ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[0] ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[3]_reduce_and_158_o )
  );
  LUT2 #(
    .INIT ( 4'h1 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n08561  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/n0153 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n0856 )
  );
  LUT5 #(
    .INIT ( 32'h6AAAAAAA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mcount_block_count_xor<4>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count [4]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count [3]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Result [4])
  );
  LUT5 #(
    .INIT ( 32'h80000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mcount_block_count_cy<4>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count [4]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mcount_block_count_cy [4])
  );
  LUT4 #(
    .INIT ( 16'h6AAA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mcount_block_count_xor<3>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Result [3])
  );
  LUT3 #(
    .INIT ( 8'h6A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mcount_block_count_xor<2>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Result [2])
  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT531  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q [9]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q [9]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [6]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<57> )

  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT521  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q [8]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q [8]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [7]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<56> )

  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT511  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q [7]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q [7]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [8]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<55> )

  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT501  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q [6]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q [6]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [9]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<54> )

  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT491  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q [5]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q [5]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [10]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<53> )

  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT481  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q [4]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q [4]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [11]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<52> )

  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT471  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q [3]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [12]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<51> )

  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT461  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q [2]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [13]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<50> )

  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT441  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [14]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<49> )

  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT431  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [15]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<48> )

  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT421  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [15]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [15]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [16]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<47> )

  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT411  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [14]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [14]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [17]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<46> )

  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT401  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [13]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [13]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [18]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<45> )

  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT391  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [12]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [12]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [19]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<44> )

  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT381  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [11]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [11]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [20]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<43> )

  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT371  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [10]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [10]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [21]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<42> )

  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT361  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [9]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [9]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [22]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<41> )

  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT351  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [8]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [8]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [23]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<40> )

  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT331  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [7]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [7]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [24]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<39> )

  );
  LUT5 #(
    .INIT ( 32'h99966966 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mxor_scr_comb<6>_xo<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [32]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [51]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [8]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/test_patt_sel_GND_24_o_equal_15_o_mmx_out ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [6])
  );
  LUT5 #(
    .INIT ( 32'h99966966 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mxor_scr_comb<24>_xo<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [14]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [33]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [26]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/test_patt_sel_GND_24_o_equal_15_o_mmx_out ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [24])
  );
  LUT5 #(
    .INIT ( 32'h99966966 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mxor_scr_comb<0>_xo<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [38]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [57]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/test_patt_sel_GND_24_o_equal_15_o_mmx_out ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [0])
  );
  LUT5 #(
    .INIT ( 32'h99966966 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mxor_scr_comb<4>_xo<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [34]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [53]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [6]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/test_patt_sel_GND_24_o_equal_15_o_mmx_out ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [4])
  );
  LUT5 #(
    .INIT ( 32'h99966966 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mxor_scr_comb<2>_xo<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [36]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [55]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [4]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/test_patt_sel_GND_24_o_equal_15_o_mmx_out ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [2])
  );
  LUT3 #(
    .INIT ( 8'h6A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mcount_block_count_xor<6>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count [6]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mcount_block_count_cy [4]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count [5]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Result [6])
  );
  LUT3 #(
    .INIT ( 8'h41 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/test_patt_sel_GND_24_o_equal_15_o12  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/test_patt_sel_GND_24_o_equal_15_o_mmx_out )
  );
  LUT3 #(
    .INIT ( 8'h72 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr110  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [0])
  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr121  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [1])
  );
  LUT2 #(
    .INIT ( 4'h6 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mcount_block_count_xor<1>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Result<1>1 )
  );
  LUT2 #(
    .INIT ( 4'h8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/new_tx_test_seed_4087 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o )
  );
  LUT2 #(
    .INIT ( 4'hD ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/reset_tx_test_en_OR_183_o1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/reset_tx_test_en_OR_183_o )
  );
  LUT2 #(
    .INIT ( 4'h6 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Maccum_tx_test_patt_seed_sel_lut<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count[6]_reduce_and_6_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Maccum_tx_test_patt_seed_sel_lut [0])
  );
  LUT3 #(
    .INIT ( 8'hFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT191  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [26]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<26> )
  );
  LUT3 #(
    .INIT ( 8'hFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT451  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [4]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<4> )
  );
  LUT3 #(
    .INIT ( 8'hFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT631  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [6]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<6> )
  );
  LUT3 #(
    .INIT ( 8'hFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT19  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<0> )
  );
  LUT6 #(
    .INIT ( 64'h0008000000080800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd1-In1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd2_4150 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd3_4151 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd1_4149 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd1-In )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFBBFEFEEEBBE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd3-In1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd2_4150 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd3_4151 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd1_4149 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd3-In )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFC944C946 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT10221  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd3_4151 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd1_4149 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd2_4150 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 )
  );
  LUT5 #(
    .INIT ( 32'h77557699 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1211  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd2_4150 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd3_4151 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd1_4149 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 )
  );
  LUT3 #(
    .INIT ( 8'h54 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT310  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [11]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<11> )
  );
  LUT3 #(
    .INIT ( 8'h54 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT45  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [12]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<12> )
  );
  LUT3 #(
    .INIT ( 8'h54 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT510  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [13]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<13> )
  );
  LUT3 #(
    .INIT ( 8'h54 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT63  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [14]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<14> )
  );
  LUT3 #(
    .INIT ( 8'h54 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT111  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [19]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<19> )
  );
  LUT3 #(
    .INIT ( 8'h54 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT131  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [20]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<20> )
  );
  LUT3 #(
    .INIT ( 8'h54 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT141  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [21]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<21> )
  );
  LUT3 #(
    .INIT ( 8'h54 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT181  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [25]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<25> )
  );
  LUT3 #(
    .INIT ( 8'h54 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT201  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [27]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<27> )
  );
  LUT3 #(
    .INIT ( 8'h54 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT211  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [28]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<28> )
  );
  LUT3 #(
    .INIT ( 8'h54 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT261  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [32]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<32> )
  );
  LUT3 #(
    .INIT ( 8'h54 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT271  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [33]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<33> )
  );
  LUT3 #(
    .INIT ( 8'h54 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT281  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [34]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<34> )
  );
  LUT3 #(
    .INIT ( 8'h54 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT291  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [35]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<35> )
  );
  LUT3 #(
    .INIT ( 8'h54 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT331  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [39]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<39> )
  );
  LUT3 #(
    .INIT ( 8'h54 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT341  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [3]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<3> )
  );
  LUT3 #(
    .INIT ( 8'h54 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT351  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [40]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<40> )
  );
  LUT3 #(
    .INIT ( 8'h54 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT361  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [41]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<41> )
  );
  LUT3 #(
    .INIT ( 8'h54 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT371  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [42]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<42> )
  );
  LUT3 #(
    .INIT ( 8'h54 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT411  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [46]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<46> )
  );
  LUT3 #(
    .INIT ( 8'h54 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT421  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [47]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<47> )
  );
  LUT3 #(
    .INIT ( 8'h54 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT431  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [48]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<48> )
  );
  LUT3 #(
    .INIT ( 8'h54 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT441  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [49]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<49> )
  );
  LUT3 #(
    .INIT ( 8'h54 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT491  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [53]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<53> )
  );
  LUT3 #(
    .INIT ( 8'h54 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT501  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [54]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<54> )
  );
  LUT3 #(
    .INIT ( 8'h54 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT511  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [55]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<55> )
  );
  LUT3 #(
    .INIT ( 8'h54 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT521  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [56]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<56> )
  );
  LUT3 #(
    .INIT ( 8'h54 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT561  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [5]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<5> )
  );
  LUT3 #(
    .INIT ( 8'h54 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT581  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [61]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<61> )
  );
  LUT3 #(
    .INIT ( 8'h54 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT591  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [62]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<62> )
  );
  LUT3 #(
    .INIT ( 8'h54 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT571  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [60]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<60> )
  );
  LUT3 #(
    .INIT ( 8'h54 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT601  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [63]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<63> )
  );
  LUT3 #(
    .INIT ( 8'h54 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT101  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT1022 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [18]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<18> )
  );
  LUT4 #(
    .INIT ( 16'hFF08 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT231  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<2> )
  );
  LUT4 #(
    .INIT ( 16'hFF08 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT541  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [58]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<58> )
  );
  LUT4 #(
    .INIT ( 16'hFF08 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT651  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [8]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<8> )
  );
  LUT6 #(
    .INIT ( 64'h2888888888888888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_invalid_cnt[4]_GND_26_o_mux_33_OUT51  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_cnt[6]_GND_26_o_mux_32_OUT22 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [4]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [2]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt[4]_GND_26_o_mux_33_OUT<4> )
  );
  LUT5 #(
    .INIT ( 32'h28888888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_invalid_cnt[4]_GND_26_o_mux_33_OUT41  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_cnt[6]_GND_26_o_mux_32_OUT22 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt[4]_GND_26_o_mux_33_OUT<3> )
  );
  LUT5 #(
    .INIT ( 32'h28888888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt_xor<3>12  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt_xor<3>11_4375 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt3 )
  );
  LUT6 #(
    .INIT ( 64'h8888888828888888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_cnt[6]_GND_26_o_mux_32_OUT71  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_cnt[6]_GND_26_o_mux_32_OUT22 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [6]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [5]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [4]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_cnt[6]_GND_26_o_mux_32_OUT411 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt[6]_GND_26_o_mux_32_OUT<6> )
  );
  LUT5 #(
    .INIT ( 32'h88882888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_cnt[6]_GND_26_o_mux_32_OUT61  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_cnt[6]_GND_26_o_mux_32_OUT22 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [4]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_cnt[6]_GND_26_o_mux_32_OUT411 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt[6]_GND_26_o_mux_32_OUT<5> )
  );
  LUT6 #(
    .INIT ( 64'h0400040000000400 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_slip_int11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1_4422 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2_4393 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2-In2_4374 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3_4394 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_806_o ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [4]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_int )
  );
  LUT3 #(
    .INIT ( 8'h28 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt_xor<1>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt_xor<3>11_4375 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt1 )
  );
  LUT3 #(
    .INIT ( 8'h28 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_invalid_cnt[4]_GND_26_o_mux_33_OUT21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_cnt[6]_GND_26_o_mux_32_OUT22 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt[4]_GND_26_o_mux_33_OUT<1> )
  );
  LUT3 #(
    .INIT ( 8'h28 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_cnt[6]_GND_26_o_mux_32_OUT21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_cnt[6]_GND_26_o_mux_32_OUT22 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt[6]_GND_26_o_mux_32_OUT<1> )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFF08080888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0142_inv1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3_4394 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2_4393 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [6]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1_4422 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_194_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0142_inv )
  );
  LUT4 #(
    .INIT ( 16'h2888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt_xor<2>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt_xor<3>11_4375 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt2 )
  );
  LUT4 #(
    .INIT ( 16'h2888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_invalid_cnt[4]_GND_26_o_mux_33_OUT31  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_cnt[6]_GND_26_o_mux_32_OUT22 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt[4]_GND_26_o_mux_33_OUT<2> )
  );
  LUT4 #(
    .INIT ( 16'h2888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_cnt[6]_GND_26_o_mux_32_OUT31  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_cnt[6]_GND_26_o_mux_32_OUT22 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt[6]_GND_26_o_mux_32_OUT<2> )
  );
  LUT3 #(
    .INIT ( 8'h7F ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_cnt[6]_GND_26_o_mux_32_OUT4111  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_cnt[6]_GND_26_o_mux_32_OUT411 )
  );
  LUT5 #(
    .INIT ( 32'h00000800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_cnt[6]_GND_26_o_mux_32_OUT221  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2_4393 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3_4394 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1_4422 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/signal_ok_reg_4222 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_1_4221 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_cnt[6]_GND_26_o_mux_32_OUT22 )
  );
  LUT2 #(
    .INIT ( 4'h6 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2-In21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2-In2_4374 )
  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_slip_done_cnt[4]_GND_26_o_MUX_394_o11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt_xor<3>11_4375 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [4]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt[4]_GND_26_o_MUX_394_o )
  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt_xor<0>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt_xor<3>11_4375 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt )
  );
  LUT3 #(
    .INIT ( 8'hFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_state[2]_GND_26_o_Mux_27_o1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1_4422 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2_4393 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3_4394 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state[2]_GND_26_o_Mux_27_o )
  );
  LUT2 #(
    .INIT ( 4'hD ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_194_o1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/signal_ok_reg_4222 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_1_4221 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_194_o )
  );
  LUT6 #(
    .INIT ( 64'h2888888888888888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mcount_ber_cnt_xor<4>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt [4]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt [2]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt [3]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mcount_ber_cnt4 )
  );
  LUT5 #(
    .INIT ( 32'h28888888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mcount_ber_cnt_xor<3>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mcount_ber_cnt3 )
  );
  LUT3 #(
    .INIT ( 8'h28 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mcount_ber_cnt_xor<1>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mcount_ber_cnt1 )
  );
  LUT4 #(
    .INIT ( 16'h2888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mcount_ber_cnt_xor<2>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mcount_ber_cnt2 )
  );
  LUT2 #(
    .INIT ( 4'h9 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In111  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In11 )
  );
  LUT3 #(
    .INIT ( 8'hFB ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mmux_timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT171  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4510 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mmux_timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT17 )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mcount_ber_cnt_xor<0>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mcount_ber_cnt )
  );
  LUT3 #(
    .INIT ( 8'hFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_state[2]_GND_27_o_Mux_25_o1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4510 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state[2]_GND_27_o_Mux_25_o )
  );
  LUT2 #(
    .INIT ( 4'h8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_state[2]_GND_27_o_Mux_27_o1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state[2]_GND_27_o_Mux_27_o )
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [38]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [57]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [2])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<10>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [28]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [12]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [47]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [12])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<11>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [27]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [13]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [46]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [13])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<12>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [26]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [14]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [45]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [14])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<13>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [25]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [44]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [15]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [15])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<14>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [24]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [43]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [16]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [16])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<15>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [42]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [17]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [23]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [17])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<16>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [41]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [18]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [22]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [18])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<17>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [21]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [40]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [19]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [19])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<18>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [39]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [20]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [20]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [20])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<19>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [21]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [38]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [19]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [21])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<1>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [56]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [37]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [3])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<20>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [18]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [22]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [37]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [22])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<21>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [17]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [23]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [36]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [23])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<22>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [16]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [24]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [35]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [24])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<23>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [15]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [34]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [25]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [25])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<24>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [14]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [33]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [26]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [26])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<25>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [13]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [32]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [27]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [27])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<26>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [12]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [31]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [28]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [28])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<27>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [11]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [30]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [29]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [29])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<28>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [10]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [30]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [29]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [30])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<29>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [28]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [31]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [9]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [31])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<2>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [55]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [36]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [4]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [4])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<30>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [27]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [32]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [8]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [32])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<31>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [26]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [33]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [7]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [33])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<32>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [25]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [34]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [6]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [34])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<33>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [35]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [24]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [35])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<34>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [23]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [4]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [36]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [36])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<35>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [22]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [37]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [37])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<36>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [21]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [38]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [38])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<37>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [39]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [20]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [39])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<38>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [40]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [19]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [40])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<39>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [18]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [41]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [41])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<3>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [35]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [54]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [5]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [5])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<40>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [42]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [17]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [42])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<41>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [16]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [43]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [4]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [43])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<42>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [44]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [15]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [44])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<43>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [14]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [45]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [6]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [45])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<44>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [13]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [46]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [7]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [46])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<45>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [12]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [47]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [8]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [47])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<46>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [48]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [11]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [9]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [48])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<47>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [49]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [10]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [10]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [49])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<48>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [9]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [50]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [11]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [50])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<49>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [8]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [51]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [12]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [51])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<4>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [53]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [6]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [34]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [6])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<50>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [7]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [52]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [13]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [52])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<51>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [6]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [53]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [14]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [53])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<52>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [5]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [54]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [15]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [54])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<53>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [4]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [55]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [16]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [55])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<54>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [56]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [17]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [3]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [56])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<55>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [57]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [18]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [57])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<56>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [58]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [19]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [58])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<57>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [59]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [20]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [59])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<58>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [21]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [60]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [60])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<59>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [61]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [22]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [3]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [61])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<5>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [33]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [52]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [7]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [7])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<60>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [62]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [4]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [23]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [62])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<61>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [24]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [63]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [5]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [63])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<62>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [64]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [6]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [25]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [64])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<63>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [26]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [65]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [7]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [65])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<6>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [32]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [51]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [8]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [8])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<7>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [31]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [50]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [9]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [9])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<8>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [49]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [10]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [30]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [10])
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_comb<9>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [48]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [11]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [29]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [11])
  );
  LUT5 #(
    .INIT ( 32'h9AAAAAAA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcount_block_count_xor<6>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [6]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcount_block_count_xor<3>11 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [4]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [5]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [3]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Result [6])
  );
  LUT3 #(
    .INIT ( 8'h6A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcount_block_count_xor<2>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Result [2])
  );
  LUT3 #(
    .INIT ( 8'h7F ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcount_block_count_xor<3>111  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcount_block_count_xor<3>11 )
  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/expected_data[63]_inv_8_OUT<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/q_541 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/q_542 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/expected_data[63]_inv_8_OUT<0> )
  );
  LUT2 #(
    .INIT ( 4'h1 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/expected_data<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/q_542 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/q_541 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/expected_data [0])
  );
  LUT2 #(
    .INIT ( 4'h6 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcount_block_count_xor<1>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Result [1])
  );
  LUT6 #(
    .INIT ( 64'h7FFE7FFE7FFE0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT27211  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [41]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [38]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [39]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [40]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_311_o ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_313_o ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT2721 )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFFFFFFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT3511  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_310_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_311_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_314_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_313_o ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_312_o ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4675 )
  );
  LUT6 #(
    .INIT ( 64'h2323030323220300 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT541  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [60]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_309_o ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4675 )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<7>2 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<58> )
  );
  LUT6 #(
    .INIT ( 64'h5555555555555554 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_ctrl_out[7]_GND_30_o_mux_323_OUT21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_301_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_310_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_311_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_302_o ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_303_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out[7]_GND_30_o_mux_323_OUT<1> )
  );
  LUT6 #(
    .INIT ( 64'h5555555555555554 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_ctrl_out[7]_GND_30_o_mux_323_OUT41  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<29>2 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_301_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_310_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_311_o ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_302_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out[7]_GND_30_o_mux_323_OUT<3> )
  );
  LUT6 #(
    .INIT ( 64'h5555555555555554 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_ctrl_out[7]_GND_30_o_mux_323_OUT81  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<29>2 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<39>2 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_301_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_315_o ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_302_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out[7]_GND_30_o_mux_323_OUT<7> )
  );
  LUT4 #(
    .INIT ( 16'hFFFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<24>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_302_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_301_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_315_o ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<29>2 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<24>1 )
  );
  LUT5 #(
    .INIT ( 32'h02000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_315_o<7>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [8]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [7]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [9]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_315_o<7>1 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_315_o )
  );
  LUT5 #(
    .INIT ( 32'h10000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_312_o<7>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [5]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [6]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [4]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_312_o<7>1 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_312_o )
  );
  LUT5 #(
    .INIT ( 32'h00400000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_311_o<7>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [6]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [4]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_310_o<7>1 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_311_o )
  );
  LUT5 #(
    .INIT ( 32'h00400000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_306_o<7>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [6]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [4]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_306_o<7>1 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_306_o )
  );
  LUT5 #(
    .INIT ( 32'h04000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_310_o<7>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [5]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [6]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [4]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_310_o<7>1 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_310_o )
  );
  LUT5 #(
    .INIT ( 32'h00000800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_307_o<7>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [6]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [4]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_306_o<7>1 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [5]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_307_o )
  );
  LUT5 #(
    .INIT ( 32'h80000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_309_o<7>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [5]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [6]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [4]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_308_o<7>1 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_309_o )
  );
  LUT5 #(
    .INIT ( 32'h00080000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_314_o<7>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [5]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [6]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [4]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_312_o<7>1 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_314_o )
  );
  LUT5 #(
    .INIT ( 32'h00400000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_305_o<7>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [5]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [6]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [4]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_304_o<7>1 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_305_o )
  );
  LUT6 #(
    .INIT ( 64'hFFFF7FFEFFFF0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT56111  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [35]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [34]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [36]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [37]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_314_o ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<56>3 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT5611 )
  );
  LUT5 #(
    .INIT ( 32'h80000002 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c4[6]_mux_239_OUT11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_GND_30_o_equal_72_o<6>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [41]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [42]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [43]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [44]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c4[6]_mux_239_OUT<0> )
  );
  LUT6 #(
    .INIT ( 64'h0C0E000A0C0C0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT531  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_1_4991 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [59]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4675 )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<7>2 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<57> )
  );
  LUT4 #(
    .INIT ( 16'hFFF8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<48>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_304_o<7>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_315_o<7>1 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<39>2 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_305_o ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<48>1 )
  );
  LUT4 #(
    .INIT ( 16'hFFF8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<29>21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_304_o<7>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_315_o<7>1 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_303_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_305_o ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<29>2 )
  );
  LUT5 #(
    .INIT ( 32'hFFFFFFFD ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c4[6]_mux_239_OUT51  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_GND_30_o_equal_72_o<6>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [41]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [42]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [44]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [43]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c4[6]_mux_239_OUT<4> )
  );
  LUT5 #(
    .INIT ( 32'hFFFFFFFD ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c6[6]_mux_261_OUT51  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_GND_30_o_equal_92_o<6>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [54]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [56]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [55]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [53]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c6[6]_mux_261_OUT<4> )
  );
  LUT5 #(
    .INIT ( 32'hFFFFFFFD ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c5[6]_mux_250_OUT51  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_GND_30_o_equal_82_o<6>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [47]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [49]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [48]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [46]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c5[6]_mux_250_OUT<4> )
  );
  LUT5 #(
    .INIT ( 32'hFFFFFFFD ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c7[6]_mux_272_OUT51  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_GND_30_o_equal_102_o<6>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [61]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [63]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [62]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [60]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c7[6]_mux_272_OUT<4> )
  );
  LUT5 #(
    .INIT ( 32'hFFFFFFFD ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c2[6]_mux_217_OUT51  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_GND_30_o_equal_52_o<6>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [26]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [28]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [27]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [25]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c2[6]_mux_217_OUT<4> )
  );
  LUT5 #(
    .INIT ( 32'hFFFFFFFD ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c0[6]_mux_195_OUT51  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_GND_30_o_equal_32_o<6>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [12]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [14]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [13]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [11]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c0[6]_mux_195_OUT<4> )
  );
  LUT5 #(
    .INIT ( 32'hFFFFFFFD ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c1[6]_mux_206_OUT51  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_GND_30_o_equal_42_o<6>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [19]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [21]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [20]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [18]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c1[6]_mux_206_OUT<4> )
  );
  LUT4 #(
    .INIT ( 16'h0008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_315_o<7>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [6]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [4]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_315_o<7>1 )
  );
  LUT5 #(
    .INIT ( 32'h00010000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_GND_30_o_equal_102_o<6>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [60]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [61]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [62]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [63]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_GND_30_o_equal_102_o<6>1 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_GND_30_o_equal_102_o )
  );
  LUT5 #(
    .INIT ( 32'h00010000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_GND_30_o_equal_92_o<6>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [53]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [54]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [55]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [56]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_GND_30_o_equal_92_o<6>1 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_GND_30_o_equal_92_o )
  );
  LUT5 #(
    .INIT ( 32'h00010000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_GND_30_o_equal_82_o<6>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [46]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [47]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [48]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [49]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_GND_30_o_equal_82_o<6>1 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_GND_30_o_equal_82_o )
  );
  LUT5 #(
    .INIT ( 32'h00010000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_GND_30_o_equal_52_o<6>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [25]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [26]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [27]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [28]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_GND_30_o_equal_52_o<6>1 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_GND_30_o_equal_52_o )
  );
  LUT5 #(
    .INIT ( 32'h00010000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_GND_30_o_equal_42_o<6>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [18]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [19]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [20]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [21]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_GND_30_o_equal_42_o<6>1 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_GND_30_o_equal_42_o )
  );
  LUT5 #(
    .INIT ( 32'h00010000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_GND_30_o_equal_32_o<6>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [11]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [12]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [13]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [14]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_GND_30_o_equal_32_o<6>1 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_GND_30_o_equal_32_o )
  );
  LUT5 #(
    .INIT ( 32'h00000800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_67_o<6>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [33]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_66_o<6>1 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [32]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [35]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [34]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_67_o )
  );
  LUT5 #(
    .INIT ( 32'h00000800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_66_o<6>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [34]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_66_o<6>1 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [33]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [32]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [35]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_66_o )
  );
  LUT5 #(
    .INIT ( 32'h00000800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_GND_30_o_equal_75_o<6>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [43]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_GND_30_o_equal_75_o<6>1 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [41]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [42]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [44]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_GND_30_o_equal_75_o )
  );
  LUT5 #(
    .INIT ( 32'h00000800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_PWR_32_o_equal_76_o<6>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [41]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_GND_30_o_equal_75_o<6>1 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [42]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [44]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [43]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_PWR_32_o_equal_76_o )
  );
  LUT4 #(
    .INIT ( 16'h8000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_118_o11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [0]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_118_o1_4700 )

  );
  LUT4 #(
    .INIT ( 16'h0008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_310_o<7>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [7]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [9]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [8]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_310_o<7>1 )
  );
  LUT4 #(
    .INIT ( 16'h0008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_312_o<7>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [8]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [7]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [9]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_312_o<7>1 )
  );
  LUT4 #(
    .INIT ( 16'h0008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_306_o<7>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [8]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [9]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [7]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_306_o<7>1 )
  );
  LUT4 #(
    .INIT ( 16'h0008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_304_o<7>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [9]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [7]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [8]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_304_o<7>1 )
  );
  LUT5 #(
    .INIT ( 32'h00010000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_308_o<7>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [4]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [5]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [6]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_308_o<7>1 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_308_o )
  );
  LUT4 #(
    .INIT ( 16'h8000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_308_o<7>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [9]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [7]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [8]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_308_o<7>1 )
  );
  LUT3 #(
    .INIT ( 8'h80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o311  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [6]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [7]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [5]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o31 )
  );
  LUT6 #(
    .INIT ( 64'h1000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_o4[3]_AND_120_o1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [5]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [7]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [8]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [6]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/o0[3]_o0[3]_OR_331_o ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_o4[3]_AND_120_o2_4709 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_o4[3]_AND_120_o )
  );
  LUT4 #(
    .INIT ( 16'hFFFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<48>21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_301_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_302_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_310_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_311_o ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<48>2 )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFFFFFFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<10>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_307_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_302_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_301_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_306_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_315_o ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<29>2 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<10>1 )
  );
  LUT3 #(
    .INIT ( 8'hFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<24>31  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_306_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_310_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_312_o ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<24>3 )
  );
  LUT3 #(
    .INIT ( 8'hFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<56>31  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_315_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_313_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_312_o ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<56>3 )
  );
  LUT3 #(
    .INIT ( 8'hFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<56>21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_311_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_301_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_310_o ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<56>2 )
  );
  LUT3 #(
    .INIT ( 8'hFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<24>21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_307_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_308_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_309_o ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<24>2 )
  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c3[6]_mux_228_OUT11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_69_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_GND_30_o_equal_62_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c3[6]_mux_228_OUT<0> )
  );
  LUT4 #(
    .INIT ( 16'hFFFD ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c6[6]_mux_261_OUT21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [6]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_GND_30_o_equal_92_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_GND_30_o_equal_93_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_PWR_32_o_equal_99_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c6[6]_mux_261_OUT<1> )
  );
  LUT5 #(
    .INIT ( 32'hFFFFFFFD ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c6[6]_mux_261_OUT71  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [6]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_PWR_32_o_equal_99_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_PWR_32_o_equal_96_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_PWR_32_o_equal_98_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_GND_30_o_equal_93_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c6[6]_mux_261_OUT<6> )
  );
  LUT5 #(
    .INIT ( 32'hFFFFFFFD ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c6[6]_mux_261_OUT81  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [6]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_PWR_32_o_equal_99_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_PWR_32_o_equal_98_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_GND_30_o_equal_93_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_PWR_32_o_equal_97_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c6[6]_mux_261_OUT<7> )
  );
  LUT4 #(
    .INIT ( 16'hFFFD ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c5[6]_mux_250_OUT21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [5]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_GND_30_o_equal_82_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_GND_30_o_equal_83_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_PWR_32_o_equal_89_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c5[6]_mux_250_OUT<1> )
  );
  LUT5 #(
    .INIT ( 32'hFFFFFFFD ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c5[6]_mux_250_OUT71  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [5]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_PWR_32_o_equal_89_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_PWR_32_o_equal_86_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_PWR_32_o_equal_88_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_GND_30_o_equal_83_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c5[6]_mux_250_OUT<6> )
  );
  LUT5 #(
    .INIT ( 32'hFFFFFFFD ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c5[6]_mux_250_OUT81  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [5]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_PWR_32_o_equal_89_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_PWR_32_o_equal_88_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_GND_30_o_equal_83_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_PWR_32_o_equal_87_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c5[6]_mux_250_OUT<7> )
  );
  LUT4 #(
    .INIT ( 16'hFFFD ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c7[6]_mux_272_OUT21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [7]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_GND_30_o_equal_102_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_GND_30_o_equal_103_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_PWR_32_o_equal_109_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c7[6]_mux_272_OUT<1> )
  );
  LUT5 #(
    .INIT ( 32'hFFFFFFFD ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c7[6]_mux_272_OUT71  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [7]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_PWR_32_o_equal_109_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_PWR_32_o_equal_106_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_PWR_32_o_equal_108_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_GND_30_o_equal_103_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c7[6]_mux_272_OUT<6> )
  );
  LUT5 #(
    .INIT ( 32'hFFFFFFFD ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c7[6]_mux_272_OUT81  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [7]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_PWR_32_o_equal_109_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_PWR_32_o_equal_108_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_GND_30_o_equal_103_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_PWR_32_o_equal_107_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c7[6]_mux_272_OUT<7> )
  );
  LUT4 #(
    .INIT ( 16'hFFFD ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c2[6]_mux_217_OUT21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_GND_30_o_equal_52_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_GND_30_o_equal_53_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_PWR_32_o_equal_59_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c2[6]_mux_217_OUT<1> )
  );
  LUT5 #(
    .INIT ( 32'hFFFFFFFD ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c2[6]_mux_217_OUT71  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_PWR_32_o_equal_59_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_PWR_32_o_equal_56_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_PWR_32_o_equal_58_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_GND_30_o_equal_53_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c2[6]_mux_217_OUT<6> )
  );
  LUT5 #(
    .INIT ( 32'hFFFFFFFD ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c2[6]_mux_217_OUT81  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_PWR_32_o_equal_59_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_PWR_32_o_equal_58_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_GND_30_o_equal_53_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_PWR_32_o_equal_57_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c2[6]_mux_217_OUT<7> )
  );
  LUT4 #(
    .INIT ( 16'hFFFD ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c4[6]_mux_239_OUT21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [4]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_GND_30_o_equal_72_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_GND_30_o_equal_73_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_PWR_32_o_equal_79_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c4[6]_mux_239_OUT<1> )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFFFFFFD ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c4[6]_mux_239_OUT61  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [4]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_GND_30_o_equal_75_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_PWR_32_o_equal_79_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_PWR_32_o_equal_76_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_GND_30_o_equal_73_o ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_PWR_32_o_equal_77_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c4[6]_mux_239_OUT<5> )
  );
  LUT5 #(
    .INIT ( 32'hFFFFFFFD ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c4[6]_mux_239_OUT71  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [4]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_PWR_32_o_equal_79_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_PWR_32_o_equal_76_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_PWR_32_o_equal_78_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_GND_30_o_equal_73_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c4[6]_mux_239_OUT<6> )
  );
  LUT5 #(
    .INIT ( 32'hFFFFFFFD ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c4[6]_mux_239_OUT81  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [4]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_PWR_32_o_equal_79_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_PWR_32_o_equal_78_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_GND_30_o_equal_73_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_PWR_32_o_equal_77_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c4[6]_mux_239_OUT<7> )
  );
  LUT4 #(
    .INIT ( 16'hFFFD ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c0[6]_mux_195_OUT21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_GND_30_o_equal_32_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_GND_30_o_equal_33_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_PWR_32_o_equal_39_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c0[6]_mux_195_OUT<1> )
  );
  LUT5 #(
    .INIT ( 32'hFFFFFFFD ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c0[6]_mux_195_OUT71  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_PWR_32_o_equal_39_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_PWR_32_o_equal_36_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_PWR_32_o_equal_38_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_GND_30_o_equal_33_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c0[6]_mux_195_OUT<6> )
  );
  LUT5 #(
    .INIT ( 32'hFFFFFFFD ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c0[6]_mux_195_OUT81  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_PWR_32_o_equal_39_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_PWR_32_o_equal_38_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_GND_30_o_equal_33_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_PWR_32_o_equal_37_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c0[6]_mux_195_OUT<7> )
  );
  LUT4 #(
    .INIT ( 16'hFFFD ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c1[6]_mux_206_OUT21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_GND_30_o_equal_42_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_GND_30_o_equal_43_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_PWR_32_o_equal_49_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c1[6]_mux_206_OUT<1> )
  );
  LUT5 #(
    .INIT ( 32'hFFFFFFFD ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c1[6]_mux_206_OUT71  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_PWR_32_o_equal_49_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_PWR_32_o_equal_46_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_PWR_32_o_equal_48_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_GND_30_o_equal_43_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c1[6]_mux_206_OUT<6> )
  );
  LUT5 #(
    .INIT ( 32'hFFFFFFFD ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c1[6]_mux_206_OUT81  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_PWR_32_o_equal_49_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_PWR_32_o_equal_48_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_GND_30_o_equal_43_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_PWR_32_o_equal_47_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c1[6]_mux_206_OUT<7> )
  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_r_type_reg[2]_GND_30_o_mux_145_OUT11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next_reg [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg[2]_GND_30_o_mux_145_OUT<0> )
  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_r_type_reg[2]_GND_30_o_mux_145_OUT21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next_reg [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg[2]_GND_30_o_mux_145_OUT<1> )
  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_r_type_reg[2]_GND_30_o_mux_145_OUT31  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next_reg [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg[2]_GND_30_o_mux_145_OUT<2> )
  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1081_inv )
  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o<1>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFE5E5E5FF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1521  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/next_state [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [56]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1102 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2_5068 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5069 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_6_4223 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<56> )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFE5E5E5FF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1171  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/next_state [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [24]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1102 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2_5068 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5069 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_6_4223 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<24> )
  );
  LUT6 #(
    .INIT ( 64'h0010001000100000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT11031  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/next_state [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/next_state [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/next_state [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_6_4223 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2_5068 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5069 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT81  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out [7]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT<7> )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT71  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out [6]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT<6> )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT61  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT<5> )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT41  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT<3> )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT31  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT<2> )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT<1> )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT191  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [17]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<17> )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT171  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [15]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<15> )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1641  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [9]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<9> )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1611  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [6]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<6> )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1601  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [63]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<63> )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT161  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [14]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<14> )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1591  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [62]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<62> )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1581  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [61]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<61> )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1571  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [60]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<60> )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1561  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<5> )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1551  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [59]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<59> )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1541  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [58]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<58> )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1531  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [57]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<57> )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1511  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [55]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<55> )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1501  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [54]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<54> )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT151  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [13]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<13> )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1491  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [53]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<53> )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1481  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [52]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<52> )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1471  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [51]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<51> )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1461  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [50]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<50> )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1441  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [49]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<49> )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1421  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [47]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<47> )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1411  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [46]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<46> )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1401  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [45]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<45> )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT141  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [12]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<12> )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1391  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [44]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<44> )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1381  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [43]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<43> )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1371  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [42]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<42> )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1361  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [41]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<41> )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1321  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [38]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<38> )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1311  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [37]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<37> )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT131  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [11]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<11> )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1271  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [33]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<33> )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1251  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [31]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<31> )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1241  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [30]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<30> )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1221  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [29]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<29> )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1211  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [28]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<28> )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1201  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [27]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<27> )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT121  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [10]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<10> )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1191  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [26]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<26> )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1181  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [25]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<25> )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1161  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [23]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<23> )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1151  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [22]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<22> )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1141  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [21]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<21> )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1131  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [20]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<20> )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1121  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<1> )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1111  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [19]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<19> )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1101  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1103 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [18]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<18> )
  );
  LUT2 #(
    .INIT ( 4'h8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT181  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [16]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<16> )
  );
  LUT2 #(
    .INIT ( 4'h8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1431  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [48]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<48> )
  );
  LUT2 #(
    .INIT ( 4'h8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1351  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [40]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<40> )
  );
  LUT2 #(
    .INIT ( 4'h8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1261  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [32]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<32> )
  );
  LUT2 #(
    .INIT ( 4'h8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT111  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<0> )
  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT51  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1231_5064 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out [4]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT<4> )
  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1281  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1231_5064 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [34]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<34> )
  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1291  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1231_5064 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [35]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<35> )
  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1301  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1231_5064 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [36]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<36> )
  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1331  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1231_5064 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [39]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<39> )
  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1341  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1231_5064 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [3]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<3> )
  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1451  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1231_5064 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [4]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<4> )
  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1621  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1231_5064 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [7]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<7> )
  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1231  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1231_5064 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<2> )
  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_6_4223 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/_n0078_inv )
  );
  LUT4 #(
    .INIT ( 16'h0001 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mcount_bit_count_eqn_4_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count [1]),
    .O(N2)
  );
  LUT6 #(
    .INIT ( 64'h0002555755570002 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mcount_bit_count_eqn_4  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count_load_en ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1498 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3_1497 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2_1496 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count [4]),
    .I5(N2),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mcount_bit_count_eqn_4_1489 )
  );
  LUT2 #(
    .INIT ( 4'hD ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1-In_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2_1496 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3_1497 ),
    .O(N4)
  );
  LUT6 #(
    .INIT ( 64'hAA2AEE6EAA2AAA6E ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1-In  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1_1495 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1341 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/n0027 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1498 ),
    .I4(N4),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1-In1 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1-In_1499 )
  );
  LUT4 #(
    .INIT ( 16'h7FFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_347_o_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1498 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3_1497 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2_1496 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1341 ),
    .O(N6)
  );
  LUT6 #(
    .INIT ( 64'h0000000000000002 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_347_o  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count [4]),
    .I5(N6),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdc_rising_bit_count[4]_AND_347_o_1631 )

  );
  LUT6 #(
    .INIT ( 64'h6FF6FFFFFFFF6FF6 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[8]_prtad[4]_equal_89_o5_SW0  (
    .I0(prtad[0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [4]),
    .I2(prtad[1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [5]),
    .I4(prtad[2]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [6]),
    .O(N8)
  );
  LUT5 #(
    .INIT ( 32'h41000041 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[8]_prtad[4]_equal_89_o5  (
    .I0(N8),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [7]),
    .I2(prtad[3]),
    .I3(prtad[4]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [8]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[8]_prtad[4]_equal_89_o )
  );
  LUT3 #(
    .INIT ( 8'hBF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2-In1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3_1497 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1341 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/n0027 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2-In1_5153 )
  );
  LUT6 #(
    .INIT ( 64'hAAAAAAAA20002222 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2-In2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2_1496 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1_1495 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[8]_prtad[4]_equal_89_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_match_1644 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1498 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2-In1_5153 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2-In2_5154 )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFF8A808E8C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2-In3  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1341 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1_1495 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1498 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3_1497 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/n0027 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2-In2_5154 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2-In )
  );
  LUT3 #(
    .INIT ( 8'h8D ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4-In_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2_1496 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1_1495 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_in_reg_1632 ),
    .O(N10)
  );
  LUT6 #(
    .INIT ( 64'hCCDF2033AAAAAAAA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4-In  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1498 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3_1497 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/n0027 ),
    .I3(N10),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2_1496 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1341 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4-In_1502 )
  );
  LUT6 #(
    .INIT ( 64'h7FFFFFFFFFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_PWR_65_o_not_equal_135_o1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [13]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [12]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [14]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [15]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_PWR_65_o_not_equal_135_o1_5156 )

  );
  LUT6 #(
    .INIT ( 64'h7FFFFFFFFFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_PWR_65_o_not_equal_135_o2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [4]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [5]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [6]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [7]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_PWR_65_o_not_equal_135_o2_5157 )

  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFBFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_PWR_65_o_not_equal_135_o3  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_PWR_65_o_not_equal_135_o2_5157 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [9]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [8]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [10]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [11]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_PWR_65_o_not_equal_135_o1_5156 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int[15]_PWR_65_o_not_equal_135_o )

  );
  LUT6 #(
    .INIT ( 64'h7FFFFFFFFFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_PWR_65_o_not_equal_129_o1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [13]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [12]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [14]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [15]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_PWR_65_o_not_equal_129_o1_5158 )

  );
  LUT6 #(
    .INIT ( 64'h7FFFFFFFFFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_PWR_65_o_not_equal_129_o2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [4]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [5]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [6]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [7]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_PWR_65_o_not_equal_129_o2_5159 )

  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFBFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_PWR_65_o_not_equal_129_o3  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_PWR_65_o_not_equal_129_o2_5159 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [9]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [8]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [10]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [11]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_PWR_65_o_not_equal_129_o1_5158 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int[15]_PWR_65_o_not_equal_129_o )

  );
  LUT6 #(
    .INIT ( 64'h7FFFFFFFFFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_PWR_65_o_not_equal_132_o1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [13]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [12]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [14]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [15]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_PWR_65_o_not_equal_132_o1_5160 )

  );
  LUT6 #(
    .INIT ( 64'h7FFFFFFFFFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_PWR_65_o_not_equal_132_o2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [4]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [5]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [6]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [7]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_PWR_65_o_not_equal_132_o2_5161 )

  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFBFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_PWR_65_o_not_equal_132_o3  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_PWR_65_o_not_equal_132_o2_5161 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [9]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [8]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [10]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [11]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_PWR_65_o_not_equal_132_o1_5160 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int[15]_PWR_65_o_not_equal_132_o )

  );
  LUT6 #(
    .INIT ( 64'hFFBFFBBB44044000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_addr<3>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/_n0084 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [1]),
    .I3(N12),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [3]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [3]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [3])
  );
  LUT6 #(
    .INIT ( 64'hFFBFFBBB44044000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_addr<4>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/_n0084 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [1]),
    .I3(N14),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [4]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [4]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [4])
  );
  LUT6 #(
    .INIT ( 64'hFFBFFBBB44044000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_addr<6>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/_n0084 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [1]),
    .I3(N16),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [6]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [6]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [6])
  );
  LUT6 #(
    .INIT ( 64'hFFBFFBBB44044000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_addr<8>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/_n0084 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [1]),
    .I3(N18),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [8]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [8]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [8])
  );
  LUT6 #(
    .INIT ( 64'hFFBFFBBB44044000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_addr<2>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/_n0084 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [1]),
    .I3(N20),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [2]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [2])
  );
  LUT6 #(
    .INIT ( 64'hBFBBFFFB04004440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_addr<1>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/_n0084 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [1]),
    .I4(N22),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [1])
  );
  LUT6 #(
    .INIT ( 64'hBFBBFFFB04004440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_addr<5>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/_n0084 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [5]),
    .I4(N24),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [5]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [5])
  );
  LUT6 #(
    .INIT ( 64'hBFBBFFFB04004440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_addr<7>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/_n0084 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [7]),
    .I4(N26),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [7]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [7])
  );
  LUT6 #(
    .INIT ( 64'hBFBBFFFB04004440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_addr<9>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/_n0084 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [9]),
    .I4(N28),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [9]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [9])
  );
  LUT6 #(
    .INIT ( 64'hBFBBFFFB04004440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_addr<10>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/_n0084 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [10]),
    .I4(N30),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [10]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [10])
  );
  LUT6 #(
    .INIT ( 64'hBFBBFFFB04004440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_addr<11>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/_n0084 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [11]),
    .I4(N32),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [11]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [11])
  );
  LUT6 #(
    .INIT ( 64'hBFBBFFFB04004440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_addr<12>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/_n0084 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [12]),
    .I4(N34),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [12]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [12])
  );
  LUT6 #(
    .INIT ( 64'hBFBBFFFB04004440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_addr<13>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/_n0084 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [13]),
    .I4(N36),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [13]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [13])
  );
  LUT6 #(
    .INIT ( 64'hBFBBFFFB04004440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_addr<14>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/_n0084 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [14]),
    .I4(N38),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [14]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [14])
  );
  LUT6 #(
    .INIT ( 64'hBFBBFFFB04004440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_addr<15>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/_n0084 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [15]),
    .I4(N40),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [15]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [15])
  );
  LUT6 #(
    .INIT ( 64'hBFBBFFFB04004440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_addr<0>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/_n0084 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [0]),
    .I4(N42),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [0])
  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o<15>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [5]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [4]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o<15> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000000001 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o<15>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [7]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [6]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [8]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [9]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [10]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [11]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o<15>1_5179 )

  );
  LUT6 #(
    .INIT ( 64'h0001000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o<15>3  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [13]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [12]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [14]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [15]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o<15> )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o<15>1_5179 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o )
  );
  LUT6 #(
    .INIT ( 64'hD555555580000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT93  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT91 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT92_5181 )

  );
  LUT6 #(
    .INIT ( 64'hFD75B931EC64A820 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT94  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [2]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT93_5182 )

  );
  LUT3 #(
    .INIT ( 8'hE4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT95  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT94_5183 )

  );
  LUT6 #(
    .INIT ( 64'hFFFFF888F888F888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT98  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1726 )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT96 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_48_o<15>1 ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT93_5182 )
,
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode1 ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT92_5181 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT97_5185 )

  );
  LUT6 #(
    .INIT ( 64'hAAAAA888A888A888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT99  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039771 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT97_5185 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_36_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_1_2/q_0_1957 ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_47_o ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT98_5186 )

  );
  LUT5 #(
    .INIT ( 32'hAA808080 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT910  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039717 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_36_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_1_2/q_0_1960 ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_42_o ),
    .I4(pma_pmd_type[2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT99_5187 )

  );
  LUT6 #(
    .INIT ( 64'h2020200000200000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT31  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039717 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_35_o<15>1_1724 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_11/q_0_1251 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_8_11/q_0_1927 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT3 )
  );
  LUT5 #(
    .INIT ( 32'hAA808080 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT32  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1726 )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[20]_GND_44_o_equal_101_o<20>1 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q [11]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [11]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT31_5189 )

  );
  LUT6 #(
    .INIT ( 64'hA888200020002000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT33  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q [11]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[20]_GND_44_o_equal_101_o<20>1 )
,
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [11]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT32_5190 )

  );
  LUT6 #(
    .INIT ( 64'hFFFFFFF8FFF8FFF8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT34  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_52_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [11]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT31_5189 )
,
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT32_5190 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_47_o ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [11]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT33_5191 )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT35  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT34_5192 )

  );
  LUT6 #(
    .INIT ( 64'hAAAA008000800080 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT36  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT34_5192 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode1 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q [11]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/q [3]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1726 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT35_5193 )

  );
  LUT5 #(
    .INIT ( 32'hD9C85140 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT37  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [11]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [11]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [11]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT36_5194 )

  );
  LUT4 #(
    .INIT ( 16'h8000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT38  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT36_5194 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT37_5195 )

  );
  LUT6 #(
    .INIT ( 64'h5555555555550040 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT39  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_11/q_0_1250 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_35_o<15>1_1724 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT35_5193 )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT37_5195 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT38_5196 )

  );
  LUT6 #(
    .INIT ( 64'h2222222220202000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT310  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/_n0398 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039771 ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT38_5196 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT33_5191 )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT3 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [11])
  );
  LUT6 #(
    .INIT ( 64'hFF8F8F8FF8888888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT132  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_48_o<15>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q [6]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1726 )
,
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q [6]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT13_5197 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT131_5198 )

  );
  LUT5 #(
    .INIT ( 32'hAA808080 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT133  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1726 )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[20]_GND_44_o_equal_101_o<20>1 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q [6]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [6]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT132_5199 )

  );
  LUT6 #(
    .INIT ( 64'hA282A08022022000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT134  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_48_o<15>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [6]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [6]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [6]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT133_5200 )

  );
  LUT6 #(
    .INIT ( 64'hA888200020002000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT135  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q [6]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[20]_GND_44_o_equal_101_o<20>1 )
,
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [6]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT134_5201 )

  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFEFFFEFFFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT136  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_35_o ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT134_5201 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT133_5200 )
,
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT132_5199 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_52_o ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [6]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT135_5202 )

  );
  LUT6 #(
    .INIT ( 64'hEAEAEAEAFFEAEAEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT137  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT135_5202 )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_47_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [6]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT131_5198 )
,
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT136_5203 )

  );
  LUT6 #(
    .INIT ( 64'hFFFFAA08AA08AA08 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT138  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039717 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT14211 )
,
    .I2(pma_pmd_type[0]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_35_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039771 ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT136_5203 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT137_5204 )

  );
  LUT5 #(
    .INIT ( 32'hAA808080 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT141  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039717 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_36_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_8_11/q_0_1927 ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT14211 )
,
    .I4(pma_pmd_type[0]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT14 )

  );
  LUT6 #(
    .INIT ( 64'hFF8F8F8FF8888888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT143  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_48_o<15>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q [7]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1726 )
,
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q [7]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT141_5206 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT142_5207 )

  );
  LUT6 #(
    .INIT ( 64'hA888200020002000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT144  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q [7]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[20]_GND_44_o_equal_101_o<20>1 )
,
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [7]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT143_5208 )

  );
  LUT5 #(
    .INIT ( 32'hD9C85140 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT145  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [7]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [7]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [7]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT144_5209 )

  );
  LUT5 #(
    .INIT ( 32'hFFF8F8F8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT147  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_48_o<15>1 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT144_5209 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT143_5208 )
,
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1726 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT145_5210 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT146_5211 )

  );
  LUT5 #(
    .INIT ( 32'hFFF8F8F8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT148  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_36_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_8_10/q_0_1926 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT146_5211 )
,
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_52_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [7]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT147_5212 )

  );
  LUT6 #(
    .INIT ( 64'hEAEAEAEAFFEAEAEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT149  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT147_5212 )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_47_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [7]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT142_5207 )
,
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT148_5213 )

  );
  LUT5 #(
    .INIT ( 32'h22202020 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT1410  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/_n0398 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT14 )
,
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT148_5213 )
,
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039771 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [7])
  );
  LUT6 #(
    .INIT ( 64'hAAAAA888A888A888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT113  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1726 )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT111 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_PWR_46_o_equal_57_o<15>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q [4]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[20]_GND_44_o_equal_101_o<20>1 )
,
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q [4]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT112_5215 )

  );
  LUT6 #(
    .INIT ( 64'hFD75B931EC64A820 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT116  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q [4]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [4]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [4]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [4]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT115_5218 )

  );
  LUT6 #(
    .INIT ( 64'hFFFFFFF8FFF8FFF8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT117  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_48_o<15>1 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT115_5218 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT114_5217 )
,
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT112_5215 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_53_o ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q [4]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT116_5219 )

  );
  LUT6 #(
    .INIT ( 64'h4040404040000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT118  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/_n0398 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039771 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [4]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_47_o ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT116_5219 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [4])
  );
  LUT4 #(
    .INIT ( 16'hFFF8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT103  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_PWR_46_o_equal_56_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_all/q [3]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_40_o ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT101_5221 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT102_5222 )

  );
  LUT6 #(
    .INIT ( 64'hFD75B931EC64A820 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT104  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [3]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT103_5223 )

  );
  LUT5 #(
    .INIT ( 32'hFFA8A8A8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT108  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1726 )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT104_5224 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT106 )
,
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_48_o<15>1 ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT103_5223 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT107_5226 )

  );
  LUT6 #(
    .INIT ( 64'hFFFFFFF8FFF8FFF8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT109  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_53_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q [3]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT102_5222 )
,
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT107_5226 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_47_o ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT108_5227 )

  );
  LUT6 #(
    .INIT ( 64'h2222200020002000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT1010  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/_n0398 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT108_5227 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039771 ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_40_o ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039717 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [3])
  );
  LUT6 #(
    .INIT ( 64'h22A800A822200020 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT121  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [5]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q [5]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [5]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT12_5228 )

  );
  LUT6 #(
    .INIT ( 64'hFD75B931EC64A820 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT126  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q [5]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [5]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [5]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [5]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT125_5232 )

  );
  LUT6 #(
    .INIT ( 64'hFFFFFFF8FFF8FFF8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT127  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_48_o<15>1 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT125_5232 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT124_5231 )
,
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT122 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_47_o ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [5]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT126_5233 )

  );
  LUT6 #(
    .INIT ( 64'hFFFF088808880888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT128  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_43_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039717 ),
    .I2(pma_pmd_type[1]),
    .I3(pma_pmd_type[2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039771 ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT126_5233 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT127_5234 )

  );
  LUT6 #(
    .INIT ( 64'hA282A08022022000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT62  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_48_o<15>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [14]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [14]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [14]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT61_5236 )

  );
  LUT6 #(
    .INIT ( 64'hFFFFFFF8FFF8FFF8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT66  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1726 )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT64_5239 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT63_5238 )
,
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT61_5236 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_35_o ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_txusrclk2_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT65_5240 )

  );
  LUT6 #(
    .INIT ( 64'hAAAAA888A888A888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT67  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT6 )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT65_5240 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_52_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [14]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_47_o ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [14]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [14])
  );
  LUT6 #(
    .INIT ( 64'hFD75B931EC64A820 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT151  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q [8]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [8]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [8]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [8]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT15_5241 )

  );
  LUT6 #(
    .INIT ( 64'hFFFFFFF8FFF8FFF8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT156  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1726 )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT154_5245 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT153_5244 )
,
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT151_5242 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_53_o ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q [8]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT155_5246 )

  );
  LUT6 #(
    .INIT ( 64'hAAAAA888A888A888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT157  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039771 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT155_5246 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_52_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [8]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_47_o ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [8]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT156_5247 )

  );
  LUT6 #(
    .INIT ( 64'h2222222220202000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT158  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/_n0398 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039717 ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_PWR_46_o_equal_60_o ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_43_o ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT156_5247 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [8])
  );
  LUT3 #(
    .INIT ( 8'hBF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .O(N44)
  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_rnw ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_addrdecode1 ),
    .I3(NlwRenamedSig_OI_pcs_resetout),
    .I4(N44),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 )
  );
  LUT6 #(
    .INIT ( 64'hA282A08022022000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT42  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_48_o<15>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [12]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [12]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [12]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT41_5249 )

  );
  LUT6 #(
    .INIT ( 64'hFFFFFFF8FFF8FFF8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT46  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1726 )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT44_5252 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT43_5251 )
,
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT41_5249 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_52_o ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [12]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT45_5253 )

  );
  LUT6 #(
    .INIT ( 64'hAAAAA888A888A888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT47  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039771 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT45_5253 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_32_12/q_0_1956 ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_47_o ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [12]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT46_5254 )

  );
  LUT6 #(
    .INIT ( 64'hAAAAAAAA00000800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT48  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT2 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [16]),
    .I2
(\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15/q_0 ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_43_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [17]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT46_5254 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [12])
  );
  LUT6 #(
    .INIT ( 64'hFD75B931EC64A820 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT161  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q [9]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [9]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [9]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [9]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT16_5255 )

  );
  LUT6 #(
    .INIT ( 64'hFFFFFFF8FFF8FFF8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT166  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1726 )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT164_5259 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT163_5258 )
,
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT161_5256 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_53_o ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q [9]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT165_5260 )

  );
  LUT6 #(
    .INIT ( 64'hAAAAA888A888A888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT167  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039771 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT165_5260 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_52_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [9]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_47_o ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [9]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT166_5261 )

  );
  LUT6 #(
    .INIT ( 64'hA282A08022022000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT52  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_48_o<15>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [13]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [13]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [13]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT51_5264 )

  );
  LUT5 #(
    .INIT ( 32'hFFFEFEFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT56  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT54_5267 )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT51_5264 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_35_o ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1726 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT52_5265 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT55_5268 )

  );
  LUT6 #(
    .INIT ( 64'hAAAAA888A888A888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT57  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039771 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT55_5268 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_52_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [13]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_47_o ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [13]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT56_5269 )

  );
  LUT6 #(
    .INIT ( 64'h2222222020222020 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT71  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_35_o<15>1_1724 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [17]),
    .I4
(\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15/q_0 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT7 )
  );
  LUT6 #(
    .INIT ( 64'hA282A08022022000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT72  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_48_o<15>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [15]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [15]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [15]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT71_5271 )

  );
  LUT6 #(
    .INIT ( 64'hFFFFFFF8FFF8FFF8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT76  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1726 )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT74_5274 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT73_5273 )
,
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT71_5271 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_52_o ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [15]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT75_5275 )

  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFF22202020 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT77  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [17]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT75_5275 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [15]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_47_o ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT7 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT76_5276 )

  );
  LUT6 #(
    .INIT ( 64'hA282A08022022000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT22  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_48_o<15>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [10]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [10]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [10]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT21 )

  );
  LUT6 #(
    .INIT ( 64'hFFFFFFF8FFF8FFF8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT26  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1726 )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT24_5281 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT23_5280 )
,
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT21 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_43_o ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_8_10/q_0_1926 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT25_5282 )

  );
  LUT6 #(
    .INIT ( 64'hAAAAA888A888A888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT27  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039771 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT25_5282 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_52_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [10]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_47_o ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [10]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT26_5283 )

  );
  LUT6 #(
    .INIT ( 64'hAAAAAAAA80000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT28  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT2 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode1 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[20]_GND_44_o_equal_101_o<20>1 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039717 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT26_5283 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [10])
  );
  LUT5 #(
    .INIT ( 32'h28200800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_4/d ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_10_0/q_0_1959 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT1 )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFF8FFF8FFF8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT12  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_reg_1_0[15]_select_26_OUT<0>2 )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT1 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_43_o ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT171 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_35_o ),
    .I5
(\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_0/q_0 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT17_5285 )

  );
  LUT6 #(
    .INIT ( 64'hFFFFFFF8FFF8FFF8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT17  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_PWR_46_o_equal_56_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_all/q [0]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT171 )
,
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT117_5288 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_45_o ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q [0]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT118_5289 )

  );
  LUT6 #(
    .INIT ( 64'hFFFFFFF8FFF8FFF8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT18  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_47_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [0]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT118_5289 )
,
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT110_5287 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_52_o ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [0]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT119_5290 )

  );
  LUT6 #(
    .INIT ( 64'hFFFFF888F888F888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT19  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_53_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q [0]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_54_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [0]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_51_o ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [0]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT120_5291 )

  );
  LUT6 #(
    .INIT ( 64'hAAAAAAAAAAAAAA80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT119  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039771 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_32_0/q_0_1954 ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT128_5292 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT119_5290 )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT120_5291 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT129_5293 )

  );
  LUT5 #(
    .INIT ( 32'hAAA8A8A8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT81  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039717 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_36_o ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_40_o ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_42_o ),
    .I4(pma_pmd_type[1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT8 )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFF8FFF8FFF8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT85  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_PWR_46_o_equal_56_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_all/q [1]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_40_o ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT83_5296 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_45_o ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT84_5297 )

  );
  LUT6 #(
    .INIT ( 64'hFFFFFFF8FFF8FFF8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT86  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_47_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [1]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT84_5297 )
,
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT82 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_52_o ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT85_5298 )

  );
  LUT6 #(
    .INIT ( 64'hFFFFF888F888F888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT87  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_53_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q [1]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_54_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_51_o ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT86_5299 )

  );
  LUT6 #(
    .INIT ( 64'hAAAAAAAAAAAAAA80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT89  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux__n039771 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_32_1/q_0_1955 ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT87_5300 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT85_5298 )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT86_5299 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT88_5301 )

  );
  LUT6 #(
    .INIT ( 64'h8000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [11]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [10]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [12]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [13]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [15]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [14]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode11_5302 )
  );
  LUT6 #(
    .INIT ( 64'h8000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode12  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [6]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [4]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [7]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [9]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [8]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode12_5303 )
  );
  LUT2 #(
    .INIT ( 4'h8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode13  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode11_5302 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode12_5303 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode1 )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFFFFFFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [15]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [14]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [13]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [12]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [11]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [10]),
    .O(N46)
  );
  LUT6 #(
    .INIT ( 64'h0000000000000001 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [6]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [4]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [9]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [8]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [7]),
    .I5(N46),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 )
  );
  LUT2 #(
    .INIT ( 4'h8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count_control_core_i_pcs_ber_count[5]_AND_185_o_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [0]),
    .O(N48)
  );
  LUT6 #(
    .INIT ( 64'h2AAAAAAAAAAAAAAA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count_control_core_i_pcs_ber_count[5]_AND_185_o  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_out_696 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [4]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [2]),
    .I5(N48),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count_control_core_i_pcs_ber_count[5]_AND_185_o_2240 )

  );
  LUT4 #(
    .INIT ( 16'h8000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count_control_core_i_pcs_error_block_count[7]_AND_186_o_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [4]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [2]),
    .O(N50)
  );
  LUT6 #(
    .INIT ( 64'h2AAAAAAAAAAAAAAA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count_control_core_i_pcs_error_block_count[7]_AND_186_o  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_out_695 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [7]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [6]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [5]),
    .I5(N50),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count_control_core_i_pcs_error_block_count[7]_AND_186_o_2239 )

  );
  LUT6 #(
    .INIT ( 64'h7FFFFFFFFFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [8]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [9]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [7]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [6]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [5]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [4]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o1_5307 )

  );
  LUT6 #(
    .INIT ( 64'h7FFFFFFFFFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [15]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [14]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [13]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o2_5308 )

  );
  LUT4 #(
    .INIT ( 16'h7FFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o3  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [11]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [12]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [10]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [0]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o3_5309 )

  );
  LUT4 #(
    .INIT ( 16'hAAA8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o4  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_out_694 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o2_5308 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o3_5309 )
,
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o1_5307 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count_control_core_i_pcs_test_pattern_error_count[15]_AND_187_o )

  );
  LUT2 #(
    .INIT ( 4'h8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/Result<6>_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [4]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [3]),
    .O(N52)
  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/_n00791_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [4]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [3]),
    .O(N54)
  );
  LUT6 #(
    .INIT ( 64'h0001000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/_n00791  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [5]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [1]),
    .I3(N54),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [6]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/_n00791_2243 )
  );
  LUT4 #(
    .INIT ( 16'hF888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd2-In1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_idle [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_was_idle_2766 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_seq [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_was_seq_2765 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd2-In1_5312 )
  );
  LUT6 #(
    .INIT ( 64'h0202722200007000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3-In1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_seq [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_was_seq_2765 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_idle [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_idle [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_was_idle_2766 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_seq [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3-In1_5313 )
  );
  LUT6 #(
    .INIT ( 64'h0100ABAA01000100 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3-In2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd2_2878 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3_2877 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3-In1_5313 )
,
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_idle [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_idle [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3-In2_5314 )
  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [64]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [65]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [7]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [4]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [3]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq<0>1_5315 )
  );
  LUT6 #(
    .INIT ( 64'h0000000000000001 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq<0>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [67]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [66]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [5]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [6]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq<0>2_5316 )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq<0>3  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/is_idle [0]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq<0>1_5315 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq<0>2_5316 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq [0])
  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq<1>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [68]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [69]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [39]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [36]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [35]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [34]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq<1>1_5317 )
  );
  LUT6 #(
    .INIT ( 64'h0000000000000001 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq<1>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [71]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [70]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [32]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [33]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [37]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [38]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq<1>2_5318 )
  );
  LUT3 #(
    .INIT ( 8'hEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq<1>3  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/is_idle [1]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq<1>1_5317 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq<1>2_5318 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq [1])
  );
  LUT6 #(
    .INIT ( 64'hBBBB3333A8882000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n08541  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_166_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1141 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[7]_tx_xgmii_data_reg1[7]_OR_155_o_3589 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_GND_22_o_equal_165_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[3]_reduce_and_158_o ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT171211 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n08541_5319 )
  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n08542  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/n0153 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n08542_5320 )
  );
  LUT6 #(
    .INIT ( 64'h0080008000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n08543  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n08542_5320 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1162 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT171_5327 ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[5]_AND_66_o )
,
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [6]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11411 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n08543_5321 )
  );
  LUT2 #(
    .INIT ( 4'h8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n08544  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n08541_5319 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n08543_5321 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n0854 )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFF55045554 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT84  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1141 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_PWR_23_o_equal_185_o_mmx_out1 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_GND_22_o_equal_181_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_GND_22_o_equal_165_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[7]_PWR_23_o_equal_182_o ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT82_5324 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT83_5325 )
  );
  LUT5 #(
    .INIT ( 32'h55554000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT174  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1141 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_166_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_GND_22_o_equal_165_o ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[7]_tx_xgmii_data_reg1[7]_OR_155_o_3589 )
,
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT171211 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT173 )
  );
  LUT5 #(
    .INIT ( 32'hFFFF2AAA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT141  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out232 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/n0141 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out142 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT143_3443 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT14 )
  );
  LUT6 #(
    .INIT ( 64'h8AAA8AAA8AAAFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT143  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1141 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_166_o ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_tx_xgmii_data_reg1[39]_OR_153_o_3588 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[3]_reduce_and_158_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11411 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [6]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT142_5332 )
  );
  LUT6 #(
    .INIT ( 64'h2A2A2AAA08080888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11111  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out232 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out142 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[0] ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/n0141 ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[15]_PWR_23_o_equal_102_o_mmx_out ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1111 )
  );
  LUT5 #(
    .INIT ( 32'hDFFBFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_347_OUT7_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [37]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [35]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [32]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [33]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [34]),
    .O(N58)
  );
  LUT6 #(
    .INIT ( 64'h04400440F4400440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_347_OUT7  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2<36>_mmx_out1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [37]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [39]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [38]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [36]),
    .I5(N58),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_347_OUT [6])
  );
  LUT4 #(
    .INIT ( 16'hDFFB ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_347_OUT6_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [37]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [35]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [32]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [33]),
    .O(N60)
  );
  LUT6 #(
    .INIT ( 64'h0000800011119111 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_347_OUT6  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [38]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [39]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [34]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [36]),
    .I4(N60),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2<36>_mmx_out1 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_347_OUT [5])
  );
  LUT5 #(
    .INIT ( 32'hDFFBFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_251_OUT7_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [5]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [2]),
    .O(N62)
  );
  LUT6 #(
    .INIT ( 64'h04400440F4400440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_251_OUT7  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2<4>_mmx_out1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [7]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [6]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [4]),
    .I5(N62),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_251_OUT [6])
  );
  LUT4 #(
    .INIT ( 16'hDFFB ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_251_OUT6_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [5]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [1]),
    .O(N64)
  );
  LUT6 #(
    .INIT ( 64'h0000800011119111 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_251_OUT6  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [6]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [7]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [4]),
    .I4(N64),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2<4>_mmx_out1 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_251_OUT [5])
  );
  LUT4 #(
    .INIT ( 16'hDFFB ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<2>_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [61]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [59]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [57]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [56]),
    .O(N66)
  );
  LUT6 #(
    .INIT ( 64'h0000008088000080 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<2>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [58]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [60]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<1>11 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [63]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [62]),
    .I5(N66),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT [5])
  );
  LUT2 #(
    .INIT ( 4'h8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<1>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [58]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [60]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<1>1_5343 )
  );
  LUT4 #(
    .INIT ( 16'h4002 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<1>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [59]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [56]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [57]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [61]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<1>2_5344 )
  );
  LUT6 #(
    .INIT ( 64'hA880808028000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<1>3  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<1>1_5343 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [62]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [63]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<1>11 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [61]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<1>2_5344 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT [6])
  );
  LUT4 #(
    .INIT ( 16'hDFFB ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<2>_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [53]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [51]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [49]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [48]),
    .O(N68)
  );
  LUT6 #(
    .INIT ( 64'h0000008088000080 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<2>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [50]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [52]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<1>11 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [55]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [54]),
    .I5(N68),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT [5])
  );
  LUT2 #(
    .INIT ( 4'h8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<1>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [50]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [52]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<1>1_5346 )
  );
  LUT4 #(
    .INIT ( 16'h4002 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<1>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [51]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [48]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [49]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [53]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<1>2_5347 )
  );
  LUT6 #(
    .INIT ( 64'hA880808028000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<1>3  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<1>1_5346 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [54]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [55]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<1>11 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [53]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<1>2_5347 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT [6])
  );
  LUT4 #(
    .INIT ( 16'hDFFB ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<2>_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [45]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [43]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [41]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [40]),
    .O(N70)
  );
  LUT6 #(
    .INIT ( 64'h0000008088000080 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<2>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [42]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [44]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<1>11 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [47]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [46]),
    .I5(N70),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT [5])
  );
  LUT2 #(
    .INIT ( 4'h8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<1>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [42]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [44]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<1>1_5349 )
  );
  LUT4 #(
    .INIT ( 16'h4002 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<1>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [43]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [40]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [41]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [45]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<1>2_5350 )
  );
  LUT6 #(
    .INIT ( 64'hA880808028000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<1>3  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<1>1_5349 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [46]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [47]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<1>11 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [45]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<1>2_5350 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT [6])
  );
  LUT4 #(
    .INIT ( 16'hDFFB ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<2>_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [29]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [27]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [25]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [24]),
    .O(N72)
  );
  LUT6 #(
    .INIT ( 64'h0000008088000080 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<2>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [26]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [28]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<1>11 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [31]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [30]),
    .I5(N72),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT [5])
  );
  LUT2 #(
    .INIT ( 4'h8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<1>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [26]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [28]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<1>1_5352 )
  );
  LUT4 #(
    .INIT ( 16'h4002 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<1>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [27]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [24]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [25]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [29]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<1>2_5353 )
  );
  LUT6 #(
    .INIT ( 64'hA880808028000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<1>3  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<1>1_5352 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [30]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [31]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<1>11 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [29]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<1>2_5353 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT [6])
  );
  LUT4 #(
    .INIT ( 16'hDFFB ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<2>_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [21]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [19]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [17]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [16]),
    .O(N74)
  );
  LUT6 #(
    .INIT ( 64'h0000008088000080 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<2>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [18]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [20]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<1>11 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [23]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [22]),
    .I5(N74),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT [5])
  );
  LUT2 #(
    .INIT ( 4'h8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<1>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [18]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [20]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<1>1_5355 )
  );
  LUT4 #(
    .INIT ( 16'h4002 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<1>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [19]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [16]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [17]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [21]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<1>2_5356 )
  );
  LUT6 #(
    .INIT ( 64'hA880808028000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<1>3  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<1>1_5355 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [22]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [23]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<1>11 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [21]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<1>2_5356 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT [6])
  );
  LUT4 #(
    .INIT ( 16'hDFFB ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<2>_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [8]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [11]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [9]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [13]),
    .O(N76)
  );
  LUT6 #(
    .INIT ( 64'h0000008088000080 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<2>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [10]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [12]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<1>11 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [15]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [14]),
    .I5(N76),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT [5])
  );
  LUT2 #(
    .INIT ( 4'h8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<1>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [10]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [12]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<1>1_5358 )
  );
  LUT4 #(
    .INIT ( 16'h4002 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<1>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [11]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [13]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [8]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [9]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<1>2_5359 )
  );
  LUT6 #(
    .INIT ( 64'hA880808028000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<1>3  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<1>1_5358 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [14]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [15]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<1>11 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [13]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<1>2_5359 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT [6])
  );
  LUT6 #(
    .INIT ( 64'h110155053333FFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT3_SW0  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>3 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d0 [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c0 [1]),
    .O(N78)
  );
  LUT5 #(
    .INIT ( 32'h54445555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT3  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>2 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d1 [1]),
    .I4(N78),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<11> )
  );
  LUT6 #(
    .INIT ( 64'h110155053333FFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT4_SW0  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>3 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d0 [2]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c0 [2]),
    .O(N80)
  );
  LUT5 #(
    .INIT ( 32'h54445555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT4  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>2 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d1 [2]),
    .I4(N80),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<12> )
  );
  LUT6 #(
    .INIT ( 64'h110155053333FFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT5_SW0  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>3 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d0 [3]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c0 [3]),
    .O(N82)
  );
  LUT5 #(
    .INIT ( 32'h54445555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT5  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>2 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d1 [3]),
    .I4(N82),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<13> )
  );
  LUT6 #(
    .INIT ( 64'h110155053333FFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT6_SW0  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>3 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d0 [4]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c0 [4]),
    .O(N84)
  );
  LUT5 #(
    .INIT ( 32'h54445555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT6  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>2 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d1 [4]),
    .I4(N84),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<14> )
  );
  LUT6 #(
    .INIT ( 64'h0001010100FFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT57_SW0  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>31 )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>111_3487 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d6 [2]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c7 [1]),
    .O(N86)
  );
  LUT5 #(
    .INIT ( 32'h54445555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT57  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>2 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d7 [2]),
    .I4(N86),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<60> )
  );
  LUT6 #(
    .INIT ( 64'h0001010100FFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT58_SW0  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>31 )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>111_3487 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d6 [3]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c7 [2]),
    .O(N88)
  );
  LUT5 #(
    .INIT ( 32'h54445555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT58  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>2 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d7 [3]),
    .I4(N88),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<61> )
  );
  LUT6 #(
    .INIT ( 64'h0001010100FFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT59_SW0  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>31 )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>111_3487 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d6 [4]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c7 [3]),
    .O(N90)
  );
  LUT5 #(
    .INIT ( 32'h54445555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT59  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>2 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d7 [4]),
    .I4(N90),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<62> )
  );
  LUT6 #(
    .INIT ( 64'h0001010100FFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT60_SW0  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>31 )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>111_3487 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d6 [5]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c7 [4]),
    .O(N92)
  );
  LUT5 #(
    .INIT ( 32'h54445555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT60  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>2 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d7 [5]),
    .I4(N92),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<63> )
  );
  LUT6 #(
    .INIT ( 64'h5554545455555555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT33  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>2 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<25>3_3486 )
,
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<25>1 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d3 [5]),
    .I5(N94),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<39> )
  );
  LUT6 #(
    .INIT ( 64'h5554545455555555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT35  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>2 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<25>3_3486 )
,
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<25>1 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d3 [6]),
    .I5(N96),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<40> )
  );
  LUT6 #(
    .INIT ( 64'h5554545455555555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT36  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>2 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<25>3_3486 )
,
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<25>1 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d3 [7]),
    .I5(N98),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<41> )
  );
  LUT6 #(
    .INIT ( 64'h010101110F0F0FFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT37_SW0  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c4 [4]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>111_3487 )
,
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d4 [0]),
    .O(N100)
  );
  LUT5 #(
    .INIT ( 32'h54445555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT37  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>2 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d5 [0]),
    .I4(N100),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<42> )
  );
  LUT4 #(
    .INIT ( 16'hAA08 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT481  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d5 [2]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [5]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT48 )

  );
  LUT5 #(
    .INIT ( 32'hAAA8A8A8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT482  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c6 [0]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<28>1 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_448_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [5]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT481_5373 )

  );
  LUT5 #(
    .INIT ( 32'h55545454 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT483  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT481_5373 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT48 )
,
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>1 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d6 [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<52> )
  );
  LUT4 #(
    .INIT ( 16'hAA08 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT531  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d5 [7]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [5]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT53 )

  );
  LUT5 #(
    .INIT ( 32'hAAA8A8A8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT532  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c6 [5]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<28>1 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_448_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [5]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT531_5375 )

  );
  LUT5 #(
    .INIT ( 32'h55545454 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT533  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT531_5375 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT53 )
,
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>1 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d6 [7]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<57> )
  );
  LUT6 #(
    .INIT ( 64'h55555155FFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT2_SW0  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [0]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [2]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c0 [0]),
    .O(N102)
  );
  LUT6 #(
    .INIT ( 64'h5540404055555555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d0 [0]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>3 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d1 [0]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>1 ),
    .I5(N102),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<10> )
  );
  LUT6 #(
    .INIT ( 64'h55555155FFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT7_SW0  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [0]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [2]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c0 [5]),
    .O(N104)
  );
  LUT6 #(
    .INIT ( 64'h5540404055555555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT7  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d0 [5]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>3 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d1 [5]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>1 ),
    .I5(N104),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<15> )
  );
  LUT6 #(
    .INIT ( 64'h55555155FFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT8_SW0  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [0]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [2]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c0 [6]),
    .O(N106)
  );
  LUT6 #(
    .INIT ( 64'h5540404055555555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT8  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d0 [6]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>3 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d1 [6]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>1 ),
    .I5(N106),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<16> )
  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [4]),
    .O(N108)
  );
  LUT6 #(
    .INIT ( 64'h0001000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [0]),
    .I3(N108),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [7]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [6]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 )

  );
  LUT3 #(
    .INIT ( 8'h80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[7]_PWR_23_o_equal_182_o<7>_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [7]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [6]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [0]),
    .O(N110)
  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[7]_PWR_23_o_equal_182_o<7>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [5]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [4]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [1]),
    .I5(N110),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[7]_PWR_23_o_equal_182_o )
  );
  LUT3 #(
    .INIT ( 8'h20 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [43]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [40]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [41]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o1_5381 )

  );
  LUT6 #(
    .INIT ( 64'h88F8888888888888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o2  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[47]_tx_xgmii_data_reg1[47]_OR_94_o2 )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o1_5381 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [25]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [24]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [27]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[31]_tx_xgmii_data_reg1[31]_OR_80_o2 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o2_5382 )

  );
  LUT6 #(
    .INIT ( 64'h2222222222222220 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o18  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_reduce_and_78_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/n0141 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o7_5383 )
,
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o12_5384 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o17_5385 )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o2_5382 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o )
  );
  LUT4 #(
    .INIT ( 16'h0800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code14  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [0]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code12 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[0] )
  );
  LUT3 #(
    .INIT ( 8'h80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_166_o<39>_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [39]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [38]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [32]),
    .O(N112)
  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_166_o<39>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [35]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [34]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [37]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [36]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [33]),
    .I5(N112),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_166_o )
  );
  LUT4 #(
    .INIT ( 16'h9451 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code51  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [33]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [39]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [37]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [38]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code5 )
  );
  LUT4 #(
    .INIT ( 16'h8001 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code52  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [39]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [37]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [36]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [38]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code51_5389 )
  );
  LUT6 #(
    .INIT ( 64'h6444200020002000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code53  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [35]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [32]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [36]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code5 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code51_5389 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [33]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code52_5390 )
  );
  LUT4 #(
    .INIT ( 16'h0800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code54  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [34]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [4]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code52_5390 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[4] )
  );
  LUT6 #(
    .INIT ( 64'h010101110F0F0FFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT40_SW0  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<28>1 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_448_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d4 [3]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 )
,
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c5 [0]),
    .O(N114)
  );
  LUT4 #(
    .INIT ( 16'h4055 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT40  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>1 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d5 [3]),
    .I3(N114),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<45> )
  );
  LUT6 #(
    .INIT ( 64'h5540404055555555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT38  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c4 [5]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<28>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d5 [1]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>1 ),
    .I5(N116),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<43> )
  );
  LUT6 #(
    .INIT ( 64'h5540404055555555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT39  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c4 [6]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<28>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d5 [2]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>1 ),
    .I5(N118),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<44> )
  );
  LUT6 #(
    .INIT ( 64'h5540404055555555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT17  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d1 [6]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<41>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d2 [6]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>1 ),
    .I5(N120),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<24> )
  );
  LUT6 #(
    .INIT ( 64'h5540404055555555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT22  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d2 [3]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<33>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d3 [3]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>1 ),
    .I5(N122),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<29> )
  );
  LUT6 #(
    .INIT ( 64'h5540404055555555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT24  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d2 [4]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<33>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d3 [4]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>1 ),
    .I5(N124),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<30> )
  );
  LUT4 #(
    .INIT ( 16'h15FF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT25_SW0  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<49>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [2]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_445_o<7>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c3 [0]),
    .O(N126)
  );
  LUT6 #(
    .INIT ( 64'h5540404055555555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT25  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d2 [5]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<33>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d3 [5]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>1 ),
    .I5(N126),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<31> )
  );
  LUT6 #(
    .INIT ( 64'h011105553333FFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT30_SW0  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<49>1 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<31>2 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_445_o<7>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d4 [2]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c3 [5]),
    .O(N128)
  );
  LUT6 #(
    .INIT ( 64'h011105553333FFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT31_SW0  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<49>1 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<31>2 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_445_o<7>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d4 [3]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c3 [6]),
    .O(N130)
  );
  LUT4 #(
    .INIT ( 16'h153F ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT55_SW0  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>1 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d6 [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d7 [1]),
    .O(N132)
  );
  LUT4 #(
    .INIT ( 16'h153F ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT61_SW0  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>1 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d6 [6]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d7 [6]),
    .O(N134)
  );
  LUT4 #(
    .INIT ( 16'h153F ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT62_SW0  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>1 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d6 [7]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d7 [7]),
    .O(N136)
  );
  LUT5 #(
    .INIT ( 32'hAAA8A8A8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT54_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c6 [6]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<28>1 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_448_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [5]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 )
,
    .O(N138)
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFF8FFF8FFF8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT54  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d6 [0]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I3(N138),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d7 [0]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>1 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<58> )
  );
  LUT6 #(
    .INIT ( 64'h0000000000000002 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>22  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>21_5404 )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_455_o ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>22_5405 )

  );
  LUT6 #(
    .INIT ( 64'h0888A88808880888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT24  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT31 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_PWR_23_o_equal_185_o_mmx_out ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_GND_22_o_equal_151_o1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_PWR_23_o_equal_185_o3 ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_166_o_mmx_out2 )
,
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [4]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1172_5470 )
  );
  LUT2 #(
    .INIT ( 4'hE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<25>3_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [0]),
    .O(N140)
  );
  LUT6 #(
    .INIT ( 64'hAAA0888088808880 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<25>3  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/o4 [0]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [2]),
    .I3(N140),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_453_o<7>1 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [4]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<25>3_3486 )

  );
  LUT6 #(
    .INIT ( 64'hAAAAAAAA80008080 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT55  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT51_5409 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT211 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT52_5410 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT53_5411 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[3]_reduce_and_158_o ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[4]_AND_64_o )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT54_5412 )
  );
  LUT3 #(
    .INIT ( 8'hEB ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[7]_tx_xgmii_data_reg1[7]_OR_155_o_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [7]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [6]),
    .O(N142)
  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[7]_tx_xgmii_data_reg1[7]_OR_155_o  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [4]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [1]),
    .I4(N142),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[7]_tx_xgmii_data_reg1[7]_OR_155_o_3589 )

  );
  LUT3 #(
    .INIT ( 8'hBF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[63]_PWR_23_o_equal_148_o<63>_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [57]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [60]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [56]),
    .O(N144)
  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[63]_PWR_23_o_equal_148_o<63>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [62]),
    .I1(N144),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [59]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [58]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [61]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [63]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[63]_PWR_23_o_equal_148_o )
  );
  LUT4 #(
    .INIT ( 16'h9451 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code81  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [57]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [63]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [61]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [62]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code8 )
  );
  LUT4 #(
    .INIT ( 16'h8001 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code82  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [63]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [61]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [60]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [62]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code81_5416 )
  );
  LUT6 #(
    .INIT ( 64'h6444200020002000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code83  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [59]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [56]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [60]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code8 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code81_5416 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [57]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code82_5417 )
  );
  LUT4 #(
    .INIT ( 16'h0800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code84  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [58]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [7]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code82_5417 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[7] )
  );
  LUT4 #(
    .INIT ( 16'h0800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code74  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [50]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [6]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code72 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[6] )
  );
  LUT3 #(
    .INIT ( 8'hEB ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_tx_xgmii_data_reg1[39]_OR_153_o_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [32]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [39]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [38]),
    .O(N148)
  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_tx_xgmii_data_reg1[39]_OR_153_o  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [36]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [37]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [34]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [33]),
    .I4(N148),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [35]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_tx_xgmii_data_reg1[39]_OR_153_o_3588 )

  );
  LUT4 #(
    .INIT ( 16'h9451 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code41  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [25]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [31]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [29]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [30]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code4 )
  );
  LUT4 #(
    .INIT ( 16'h8001 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code42  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [31]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [29]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [28]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [30]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code41_5421 )
  );
  LUT6 #(
    .INIT ( 64'h6444200020002000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code43  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [27]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [24]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [28]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code4 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code41_5421 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [25]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code42_5422 )
  );
  LUT4 #(
    .INIT ( 16'h0800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code44  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [26]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [3]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code42_5422 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[3] )
  );
  LUT3 #(
    .INIT ( 8'h7F ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[23]_PWR_23_o_equal_110_o<23>_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [23]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [22]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [16]),
    .O(N150)
  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[23]_PWR_23_o_equal_110_o<23>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [20]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [18]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [21]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [17]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [19]),
    .I5(N150),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[23]_PWR_23_o_equal_110_o )
  );
  LUT4 #(
    .INIT ( 16'h9451 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code31  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [17]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [23]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [21]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [22]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code3 )
  );
  LUT4 #(
    .INIT ( 16'h8001 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code32  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [22]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [21]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [20]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [23]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code31_5425 )
  );
  LUT6 #(
    .INIT ( 64'h6444200020002000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code33  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [19]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [16]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [20]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code3 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code31_5425 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [17]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code32_5426 )
  );
  LUT4 #(
    .INIT ( 16'h0800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code34  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [18]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [2]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code32_5426 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[2] )
  );
  LUT3 #(
    .INIT ( 8'hBF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[15]_PWR_23_o_equal_102_o<15>_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [9]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [15]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [8]),
    .O(N152)
  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[15]_PWR_23_o_equal_102_o<15>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [11]),
    .I1(N152),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [14]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [13]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [10]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [12]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[15]_PWR_23_o_equal_102_o )
  );
  LUT4 #(
    .INIT ( 16'h9451 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [9]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [15]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [13]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [14]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code2 )
  );
  LUT4 #(
    .INIT ( 16'h8001 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code22  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [14]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [13]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [12]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [15]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code21_5429 )
  );
  LUT6 #(
    .INIT ( 64'h6444200020002000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code23  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [11]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [8]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [12]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code2 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code21_5429 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [9]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code22_5430 )
  );
  LUT4 #(
    .INIT ( 16'h0800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code24  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [10]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [1]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code22_5430 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[1] )
  );
  LUT6 #(
    .INIT ( 64'h9BBA9BBAFFFF9BBA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<4>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [14]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [13]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [15]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [12]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [8]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [9]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<4>1_5431 )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFFF5551 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<4>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [11]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [8]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [12]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [13]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<4>3 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<4>1_5431 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT [3])
  );
  LUT4 #(
    .INIT ( 16'h2AEE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<5>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [15]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [8]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [14]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [9]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<5>1_5432 )
  );
  LUT4 #(
    .INIT ( 16'h1151 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<5>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [11]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [8]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [12]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [15]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<5>2_5433 )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFFFFF76 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<5>3  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [12]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [13]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [14]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<4>3 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<5>2_5433 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<5>1_5432 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT [2])
  );
  LUT5 #(
    .INIT ( 32'h7F6EFF6E ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<6>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [61]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [63]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [60]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [62]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [56]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<6>1_5434 )
  );
  LUT5 #(
    .INIT ( 32'h04545555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<6>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [59]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [60]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [63]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [62]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [57]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<6>2_5435 )
  );
  LUT3 #(
    .INIT ( 8'hFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<6>3  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<4>3 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<6>1_5434 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<6>2_5435 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT [1])
  );
  LUT6 #(
    .INIT ( 64'h2A2AFF2AEEEEFFEE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<5>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [63]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [56]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [62]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [61]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [60]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [57]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<5>1_5436 )
  );
  LUT6 #(
    .INIT ( 64'h0E0E0E0E0EAEFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<5>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [60]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [62]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [61]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [63]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [56]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [59]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<5>2_5437 )
  );
  LUT3 #(
    .INIT ( 8'hFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<5>3  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<4>3 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<5>2_5437 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<5>1_5436 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT [2])
  );
  LUT6 #(
    .INIT ( 64'hB2B2B2FFFFB2FFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<3>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [63]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [62]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [61]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [59]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [57]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [60]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<3>1_5438 )
  );
  LUT4 #(
    .INIT ( 16'h222A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<3>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [62]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [59]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [63]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [61]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<3>2_5439 )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFDFFDDD ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<3>3  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [58]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<3>2_5439 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [56]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [60]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [57]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<3>1_5438 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT [4])
  );
  LUT5 #(
    .INIT ( 32'h7F6EFF6E ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<6>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [53]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [55]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [52]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [54]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [48]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<6>1_5440 )
  );
  LUT5 #(
    .INIT ( 32'h04545555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<6>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [51]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [52]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [55]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [54]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [49]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<6>2_5441 )
  );
  LUT3 #(
    .INIT ( 8'hFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<6>3  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<4>3 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<6>1_5440 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<6>2_5441 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT [1])
  );
  LUT6 #(
    .INIT ( 64'h2A2AFF2AEEEEFFEE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<5>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [55]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [48]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [54]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [53]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [52]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [49]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<5>1_5442 )
  );
  LUT6 #(
    .INIT ( 64'h0E0E0E0E0EAEFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<5>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [52]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [54]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [53]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [55]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [48]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [51]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<5>2_5443 )
  );
  LUT3 #(
    .INIT ( 8'hFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<5>3  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<4>3 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<5>2_5443 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<5>1_5442 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT [2])
  );
  LUT6 #(
    .INIT ( 64'hB2B2B2FFFFB2FFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<3>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [55]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [54]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [53]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [51]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [49]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [52]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<3>1_5444 )
  );
  LUT4 #(
    .INIT ( 16'h222A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<3>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [54]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [51]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [55]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [53]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<3>2_5445 )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFDFFDDD ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<3>3  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [50]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<3>2_5445 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [48]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [52]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [49]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<3>1_5444 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT [4])
  );
  LUT5 #(
    .INIT ( 32'h7F6EFF6E ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<6>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [45]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [47]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [44]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [46]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [40]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<6>1_5446 )
  );
  LUT5 #(
    .INIT ( 32'h04545555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<6>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [43]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [44]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [47]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [46]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [41]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<6>2_5447 )
  );
  LUT3 #(
    .INIT ( 8'hFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<6>3  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<4>3 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<6>1_5446 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<6>2_5447 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT [1])
  );
  LUT6 #(
    .INIT ( 64'h2A2AFF2AEEEEFFEE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<5>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [47]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [40]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [46]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [45]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [44]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [41]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<5>1_5448 )
  );
  LUT6 #(
    .INIT ( 64'h0E0E0E0E0EAEFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<5>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [44]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [46]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [45]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [47]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [40]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [43]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<5>2_5449 )
  );
  LUT3 #(
    .INIT ( 8'hFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<5>3  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<4>3 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<5>2_5449 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<5>1_5448 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT [2])
  );
  LUT6 #(
    .INIT ( 64'hB2B2B2FFFFB2FFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<3>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [47]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [46]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [45]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [43]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [41]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [44]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<3>1_5450 )
  );
  LUT4 #(
    .INIT ( 16'h222A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<3>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [46]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [43]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [47]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [45]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<3>2_5451 )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFDFFDDD ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<3>3  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [42]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<3>2_5451 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [40]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [44]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [41]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<3>1_5450 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT [4])
  );
  LUT5 #(
    .INIT ( 32'h7F6EFF6E ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<6>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [29]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [31]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [28]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [30]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [24]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<6>1_5452 )
  );
  LUT5 #(
    .INIT ( 32'h04545555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<6>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [27]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [28]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [31]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [30]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [25]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<6>2_5453 )
  );
  LUT3 #(
    .INIT ( 8'hFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<6>3  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<4>3 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<6>1_5452 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<6>2_5453 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT [1])
  );
  LUT6 #(
    .INIT ( 64'h2A2AFF2AEEEEFFEE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<5>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [31]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [24]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [30]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [29]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [28]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [25]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<5>1_5454 )
  );
  LUT6 #(
    .INIT ( 64'h0E0E0E0E0EAEFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<5>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [28]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [30]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [29]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [31]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [24]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [27]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<5>2_5455 )
  );
  LUT3 #(
    .INIT ( 8'hFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<5>3  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<4>3 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<5>2_5455 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<5>1_5454 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT [2])
  );
  LUT6 #(
    .INIT ( 64'hB2B2B2FFFFB2FFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<3>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [31]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [30]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [29]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [27]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [25]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [28]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<3>1_5456 )
  );
  LUT4 #(
    .INIT ( 16'h222A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<3>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [30]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [27]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [31]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [29]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<3>2_5457 )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFDFFDDD ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<3>3  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [26]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<3>2_5457 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [24]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [28]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [25]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<3>1_5456 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT [4])
  );
  LUT5 #(
    .INIT ( 32'h7F6EFF6E ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<6>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [21]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [23]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [20]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [22]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [16]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<6>1_5458 )
  );
  LUT5 #(
    .INIT ( 32'h04545555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<6>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [19]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [20]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [23]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [22]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [17]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<6>2_5459 )
  );
  LUT3 #(
    .INIT ( 8'hFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<6>3  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<4>3 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<6>1_5458 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<6>2_5459 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT [1])
  );
  LUT6 #(
    .INIT ( 64'h2A2AFF2AEEEEFFEE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<5>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [23]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [16]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [22]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [21]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [20]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [17]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<5>1_5460 )
  );
  LUT6 #(
    .INIT ( 64'h0E0E0E0E0EAEFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<5>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [20]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [22]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [21]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [23]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [16]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [19]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<5>2_5461 )
  );
  LUT3 #(
    .INIT ( 8'hFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<5>3  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<4>3 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<5>2_5461 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<5>1_5460 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT [2])
  );
  LUT6 #(
    .INIT ( 64'hB2B2B2FFFFB2FFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<3>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [23]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [22]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [21]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [19]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [17]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [20]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<3>1_5462 )
  );
  LUT4 #(
    .INIT ( 16'h222A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<3>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [22]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [19]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [23]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [21]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<3>2_5463 )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFDFFDDD ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<3>3  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [18]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<3>2_5463 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [16]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [20]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [17]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<3>1_5462 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT [4])
  );
  LUT5 #(
    .INIT ( 32'h7F6EFF6E ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<6>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [13]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [15]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [12]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [14]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [8]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<6>1_5464 )
  );
  LUT5 #(
    .INIT ( 32'h04545555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<6>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [11]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [12]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [15]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [14]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [9]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<6>2_5465 )
  );
  LUT3 #(
    .INIT ( 8'hFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<6>3  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<4>3 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<6>1_5464 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<6>2_5465 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT [1])
  );
  LUT6 #(
    .INIT ( 64'h8A8A8AFFFF8AFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<3>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [13]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [15]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [14]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [9]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [11]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [8]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<3>1_5466 )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFEE772AFFEE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<3>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [14]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [11]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [13]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [15]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [12]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [8]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<3>2_5467 )
  );
  LUT3 #(
    .INIT ( 8'hFB ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<3>3  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<3>2_5467 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [10]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT<3>1_5466 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_274_OUT [4])
  );
  LUT6 #(
    .INIT ( 64'hBBB3BBB3BBB38880 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1172  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out142 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_reduce_and_78_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/n0141 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[0] ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1711 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT117 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1171_5469 )
  );
  LUT5 #(
    .INIT ( 32'hFFFFA888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1178  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/n0153 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1171_5469 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1162 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1176_5473 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/PWR_23_o_GND_22_o_mux_218_OUT [1])
  );
  LUT3 #(
    .INIT ( 8'h7F ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_126_o<39>_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [39]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [38]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [32]),
    .O(N154)
  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_126_o<39>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [36]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [34]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [37]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [33]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [35]),
    .I5(N154),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_126_o )
  );
  LUT3 #(
    .INIT ( 8'h7F ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/n0141<7>_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [7]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [6]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [0]),
    .O(N156)
  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/n0141<7>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [4]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [5]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [3]),
    .I5(N156),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/n0141 )
  );
  LUT6 #(
    .INIT ( 64'h5555440455555555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT113  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT232 ),
    .I2(N158),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[2]_AND_57_o )
,
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11322 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/n0153 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/PWR_23_o_GND_22_o_mux_218_OUT [0])
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFF8FFF8FFF8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT19  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d3 [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I3(N166),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<33>1 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d2 [0]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<26> )
  );
  LUT6 #(
    .INIT ( 64'h9BBA9BBAFFFF9BBA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<4>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [62]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [61]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [63]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [60]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [56]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [57]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<4>1_5479 )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFFF5551 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<4>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [59]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [56]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [60]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [61]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<4>3 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT<4>1_5479 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_412_OUT [3])
  );
  LUT6 #(
    .INIT ( 64'h9BBA9BBAFFFF9BBA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<4>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [54]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [53]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [55]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [52]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [48]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [49]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<4>1_5480 )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFFF5551 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<4>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [51]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [48]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [52]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [53]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<4>3 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT<4>1_5480 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_391_OUT [3])
  );
  LUT6 #(
    .INIT ( 64'h9BBA9BBAFFFF9BBA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<4>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [46]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [45]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [47]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [44]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [40]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [41]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<4>1_5481 )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFFF5551 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<4>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [43]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [40]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [44]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [45]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<4>3 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT<4>1_5481 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_370_OUT [3])
  );
  LUT6 #(
    .INIT ( 64'h9BBA9BBAFFFF9BBA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<4>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [30]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [29]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [31]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [28]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [24]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [25]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<4>1_5482 )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFFF5551 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<4>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [27]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [24]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [28]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [29]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<4>3 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT<4>1_5482 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_316_OUT [3])
  );
  LUT6 #(
    .INIT ( 64'h9BBA9BBAFFFF9BBA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<4>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [22]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [21]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [23]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [20]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [16]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [17]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<4>1_5483 )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFFF5551 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<4>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [19]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [16]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [20]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [21]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<4>3 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT<4>1_5483 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/GND_22_o_GND_22_o_mux_295_OUT [3])
  );
  LUT5 #(
    .INIT ( 32'hFFFF2000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT203  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_GND_22_o_equal_151_o1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [4]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_PWR_23_o_equal_185_o3 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[7]_PWR_23_o_equal_182_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT92 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT202 )
  );
  LUT6 #(
    .INIT ( 64'h4444400055555555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT205  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[4]_AND_64_o )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT31 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT203_5485 ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_PWR_23_o_equal_185_o_mmx_out ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT202 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT211 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT204_5486 )
  );
  LUT5 #(
    .INIT ( 32'h00010000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out14111  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [47]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [46]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [45]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [44]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [42]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out14111_5487 )
  );
  LUT5 #(
    .INIT ( 32'h40404000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out14112  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [43]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [41]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [40]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out14111_5487 ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[47]_tx_xgmii_data_reg1[47]_OR_94_o2 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out14112_5488 )
  );
  LUT4 #(
    .INIT ( 16'h0800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out14113  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [44]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [43]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [40]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [42]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out14113_5489 )
  );
  LUT5 #(
    .INIT ( 32'h82202202 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out14114  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out14113_5489 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [41]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [47]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [45]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [46]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out14114_5490 )
  );
  LUT6 #(
    .INIT ( 64'h5540404055555555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT10  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d1 [0]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<41>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d2 [0]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>1 ),
    .I5(N168),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<18> )
  );
  LUT6 #(
    .INIT ( 64'h5540404055555555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d1 [1]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<41>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d2 [1]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>1 ),
    .I5(N170),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<19> )
  );
  LUT6 #(
    .INIT ( 64'h5540404055555555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT13  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d1 [2]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<41>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d2 [2]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>1 ),
    .I5(N172),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<20> )
  );
  LUT6 #(
    .INIT ( 64'h5540404055555555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT14  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d1 [3]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<41>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d2 [3]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>1 ),
    .I5(N174),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<21> )
  );
  LUT6 #(
    .INIT ( 64'h5540404055555555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT18  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d1 [7]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<41>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d2 [7]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>1 ),
    .I5(N176),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<25> )
  );
  LUT6 #(
    .INIT ( 64'h5540404055555555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT20  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d2 [1]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<33>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d3 [1]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>1 ),
    .I5(N178),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<27> )
  );
  LUT6 #(
    .INIT ( 64'h5540404055555555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d2 [2]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<33>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d3 [2]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>1 ),
    .I5(N180),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<28> )
  );
  LUT4 #(
    .INIT ( 16'h0155 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT41_SW0  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>2 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d4 [4]),
    .O(N182)
  );
  LUT6 #(
    .INIT ( 64'h5540404055555555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT41  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d5 [4]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c5 [1]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<17>1 ),
    .I5(N182),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<46> )
  );
  LUT4 #(
    .INIT ( 16'h0155 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT42_SW0  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>2 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d4 [5]),
    .O(N184)
  );
  LUT6 #(
    .INIT ( 64'h5540404055555555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT42  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d5 [5]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c5 [2]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<17>1 ),
    .I5(N184),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<47> )
  );
  LUT4 #(
    .INIT ( 16'h0155 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT43_SW0  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>2 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d4 [6]),
    .O(N186)
  );
  LUT6 #(
    .INIT ( 64'h5540404055555555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT43  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d5 [6]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c5 [3]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<17>1 ),
    .I5(N186),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<48> )
  );
  LUT4 #(
    .INIT ( 16'h0155 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT44_SW0  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>2 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d4 [7]),
    .O(N188)
  );
  LUT6 #(
    .INIT ( 64'h5540404055555555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT44  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d5 [7]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c5 [4]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<17>1 ),
    .I5(N188),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<49> )
  );
  LUT5 #(
    .INIT ( 32'h11015555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT49_SW0  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>2 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [5]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d5 [3]),
    .O(N190)
  );
  LUT6 #(
    .INIT ( 64'h5540404055555555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT49  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d6 [3]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c6 [1]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>2 ),
    .I5(N190),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<53> )
  );
  LUT5 #(
    .INIT ( 32'h11015555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT50_SW0  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>2 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [5]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d5 [4]),
    .O(N192)
  );
  LUT6 #(
    .INIT ( 64'h5540404055555555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT50  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d6 [4]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c6 [2]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>2 ),
    .I5(N192),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<54> )
  );
  LUT5 #(
    .INIT ( 32'h11015555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT51_SW0  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>2 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [5]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d5 [5]),
    .O(N194)
  );
  LUT6 #(
    .INIT ( 64'h5540404055555555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT51  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d6 [5]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c6 [3]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>2 ),
    .I5(N194),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<55> )
  );
  LUT5 #(
    .INIT ( 32'h11015555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT52_SW0  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>2 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [5]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d5 [6]),
    .O(N196)
  );
  LUT6 #(
    .INIT ( 64'h5540404055555555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT52  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d6 [6]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c6 [4]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>2 ),
    .I5(N196),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<56> )
  );
  LUT6 #(
    .INIT ( 64'hFFFFEEECFFFF2220 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT114  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT211 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[4]_AND_64_o )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11121 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT111_5507 ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[3]_AND_61_o )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[47]_PWR_23_o_equal_134_o_mmx_out1 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT112_5508 )
  );
  LUT6 #(
    .INIT ( 64'h5540404055555555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT9  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d0 [7]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>3 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d1 [7]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>1 ),
    .I5(N198),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<17> )
  );
  LUT6 #(
    .INIT ( 64'h5540404055555555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT15  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d1 [4]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<41>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d2 [4]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>1 ),
    .I5(N200),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<22> )
  );
  LUT6 #(
    .INIT ( 64'h5540404055555555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT16  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d1 [5]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<41>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d2 [5]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>1 ),
    .I5(N202),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<23> )
  );
  LUT6 #(
    .INIT ( 64'h5540404055555555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT26  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d2 [6]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<33>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d3 [6]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>1 ),
    .I5(N204),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<32> )
  );
  LUT6 #(
    .INIT ( 64'h5540404055555555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT27  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d2 [7]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<33>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d3 [7]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>1 ),
    .I5(N206),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<33> )
  );
  LUT3 #(
    .INIT ( 8'hFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out1_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [6]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [0]),
    .O(N214)
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFFFFFFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [4]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [5]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [7]),
    .I5(N214),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/n0153 )
  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT92  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [1]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT9 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<17> )

  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT82  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [0]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT8 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<16> )

  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT72  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [15]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [15]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT7 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<15> )

  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT62  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [14]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [14]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT6 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<14> )

  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT52  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [13]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [13]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT5 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<13> )

  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT582  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [9]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [9]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT58 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<9> )
  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT572  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [8]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [8]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT57 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<8> )
  );
  LUT5 #(
    .INIT ( 32'h99966966 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT561  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [17]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [58]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/test_patt_sel_GND_24_o_equal_15_o_mmx_out ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT56 )

  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT562  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [7]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [7]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT56 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<7> )
  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT552  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [6]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [6]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT55 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<6> )
  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT542  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [5]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [5]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT54 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<5> )
  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT452  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [4]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [4]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT45 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<4> )
  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT42  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [12]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [12]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT4 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<12> )

  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT342  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [3]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT34 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<3> )
  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT322  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [6]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [6]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT32_5528 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<38> )

  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT312  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [5]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [5]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT31_5529 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<37> )

  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT32  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [11]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [11]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT3 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<11> )

  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT302  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [4]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [4]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT30 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<36> )

  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT292  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [3]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT29 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<35> )

  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT282  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [2]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT28 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<34> )

  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT272  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [1]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT27 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<33> )

  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT262  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [0]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT26 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<32> )

  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT252  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [15]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [15]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT25 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<31> )

  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT242  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [14]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [14]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT24 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<30> )

  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT232  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [2]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT23 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<2> )
  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT222  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [13]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [13]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT22_5539 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<29> )

  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT212  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [12]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [12]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT21_5540 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<28> )

  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT22  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [10]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [10]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT2 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<10> )

  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT202  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [11]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [11]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT20 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<27> )

  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT192  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [10]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [10]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT19 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<26> )

  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT182  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [9]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [9]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT18 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<25> )

  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT172  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [8]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [8]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT17 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<24> )

  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT162  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [7]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [7]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT16 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<23> )

  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT152  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [6]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [6]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT15 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<22> )

  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT142  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [5]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [5]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT14 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<21> )

  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT132  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [4]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [4]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT13 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<20> )

  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT122  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [1]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT12_5550 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<1> )
  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT112  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [3]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT11_5551 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<19> )

  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT12  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [0]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT1 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<0> )
  );
  LUT6 #(
    .INIT ( 64'h5DF77FD508A22A80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT102  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_en_new_tx_test_seed_AND_83_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q [2]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT10 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT<18> )

  );
  LUT2 #(
    .INIT ( 4'h8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/out_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count [0]),
    .O(N216)
  );
  LUT6 #(
    .INIT ( 64'h8000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/out  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count [5]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count [4]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count [6]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count [2]),
    .I5(N216),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count[6]_reduce_and_6_o )
  );
  LUT2 #(
    .INIT ( 4'h7 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt_xor<4>1_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [0]),
    .O(N218)
  );
  LUT6 #(
    .INIT ( 64'h8888A88888882888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt_xor<4>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt_xor<3>11_4375 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [4]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_cnt [3]),
    .I4(N218),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_int ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt4 )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFBFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1-In_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2_4393 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3_4394 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [6]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [1]),
    .O(N220)
  );
  LUT6 #(
    .INIT ( 64'h44444444444444E4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1-In  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1_4422 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2-In2_4374 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [4]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [3]),
    .I5(N220),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1-In_4395 )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFF5551FFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2-In2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2-In2_4374 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_806_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [4]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/test_sh_4421 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [6]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2-In1_5557 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2-In3_5558 )
  );
  LUT3 #(
    .INIT ( 8'h01 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2-In3  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1_4422 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3_4394 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_4420 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2-In4_5559 )
  );
  LUT6 #(
    .INIT ( 64'hFA8ADA8AAA8A8A8A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2-In4  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2_4393 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2-In4_5559 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3_4394 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2-In3_5558 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/test_sh_4421 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2-In )
  );
  LUT2 #(
    .INIT ( 4'h7 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt_xor<3>11_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2_4393 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3_4394 ),
    .O(N222)
  );
  LUT6 #(
    .INIT ( 64'hEFEEFFFFFFFFEFEE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt_xor<3>11  (
    .I0(N222),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1_4422 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [4]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_806_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mcount_slip_done_cnt_xor<3>11_4375 )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFDFFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3-In1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [4]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [3]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [6]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3-In1_5561 )
  );
  LUT6 #(
    .INIT ( 64'hFFA8FFAA88A8AAAA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3-In3  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1_4422 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/slip_done_4420 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3_4394 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2_4393 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3-In2_5562 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3-In )
  );
  LUT2 #(
    .INIT ( 4'h7 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0174_inv_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3_4394 ),
    .O(N224)
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFF11111115 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0174_inv  (
    .I0(N224),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2_4393 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2-In2_4374 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [4]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1_4422 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_194_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/_n0174_inv_4399 )
  );
  LUT3 #(
    .INIT ( 8'h80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1-In1_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt [0]),
    .O(N226)
  );
  LUT6 #(
    .INIT ( 64'hAA000000FF3CFF3C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1-In1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ),
    .I4(N226),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_done_INV_125_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1-In1_4425 )
  );
  LUT6 #(
    .INIT ( 64'hFF57AA02AA02AA02 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_test_sh_4485 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4510 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In1_5565 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In2_5566 )
  );
  LUT6 #(
    .INIT ( 64'hC4C44444F4C4F444 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In3  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_test_sh_4485 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In11 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_done_INV_125_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In3_5567 )
  );
  LUT5 #(
    .INIT ( 32'h7FFF0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In4  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In3_5567 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In4_5568 )
  );
  LUT6 #(
    .INIT ( 64'h44F444F444F400F0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In5  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/q_543 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_806_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In2_5566 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In4_5568 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In )
  );
  LUT2 #(
    .INIT ( 4'hD ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2-In_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/q_543 ),
    .O(N228)
  );
  LUT6 #(
    .INIT ( 64'h222A22EE222A222A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2-In  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1-In1_4425 ),
    .I3(N228),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mmux_timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT17 )
,
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_test_sh_4485 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2-In_4465 )
  );
  LUT6 #(
    .INIT ( 64'hFF08080808080808 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1-In2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4510 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_done_INV_125_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1-In1_4425 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1-In2_5570 )
  );
  LUT5 #(
    .INIT ( 32'h44F400F0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1-In3  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/q_543 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_806_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4510 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1-In2_5570 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1-In )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFFFFFFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/out1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [7]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [6]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [9]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [8]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [11]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [10]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/out )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFFFFFFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/out2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [5]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [4]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/out1_5572 )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFFFFFFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/out3  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [14]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [15]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [12]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [13]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/out1_5572 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/out ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_done_INV_125_o )
  );
  LUT2 #(
    .INIT ( 4'h8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mmux_err_block_count_inc_in_GND_28_o_MUX_424_o1_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/q_543 ),
    .O(N230)
  );
  LUT6 #(
    .INIT ( 64'h08FF080008000800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mmux_err_block_count_inc_in_GND_28_o_MUX_424_o1  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/rx_66_enc[65]_expected_data[63]_not_equal_9_o ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/rx_66_enc[65]_expected_data[63]_not_equal_7_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/ignore_next_mismatch_4671 ),
    .I3(N230),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2_5068 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5069 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/err_block_count_inc_in_GND_28_o_MUX_424_o )
  );
  LUT3 #(
    .INIT ( 8'hFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/_n0062_inv_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [4]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [3]),
    .O(N234)
  );
  LUT6 #(
    .INIT ( 64'h0000000000000002 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/_n0062_inv  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [6]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [1]),
    .I5(N234),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/_n0062_inv_4665 )
  );
  LUT6 #(
    .INIT ( 64'hFEFEFEFAFCFCFCF0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT421  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_7_4982 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [57]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_307_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_308_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_309_o ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<16>2_4714 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT42_5575 )
  );
  LUT6 #(
    .INIT ( 64'hFEFEFEFAFCFCFCF0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT411  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_6_4981 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [56]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_307_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_308_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_309_o ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<16>2_4714 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT41 )
  );
  LUT6 #(
    .INIT ( 64'hFEFEFEFAFCFCFCF0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT401  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_5_4980 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [55]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_307_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_308_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_309_o ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<16>2_4714 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT40 )
  );
  LUT6 #(
    .INIT ( 64'hFEFEFEFAFCFCFCF0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT391  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_4_4979 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [54]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_307_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_308_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_309_o ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<16>2_4714 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT39 )
  );
  LUT6 #(
    .INIT ( 64'hFEFEFEFAFCFCFCF0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT381  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_3_4978 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [53]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_307_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_308_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_309_o ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<16>2_4714 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT38 )
  );
  LUT6 #(
    .INIT ( 64'hFEFEFEFAFCFCFCF0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_0_4976 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [50]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_307_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_308_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_309_o ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<16>2_4714 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT35 )
  );
  LUT6 #(
    .INIT ( 64'h5555444044404440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT361  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [51]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_309_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_308_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c5_1_4977 ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<16>2_4714 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT36 )
  );
  LUT4 #(
    .INIT ( 16'h5444 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT362  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT36 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [43]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4675 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<41> )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFF8FFF8FFF8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT30_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [38]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_314_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_311_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_313_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [46]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<24>2 ),
    .O(N238)
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFF8FFF8FFF8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT29_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [37]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_314_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_311_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_313_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [45]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<24>2 ),
    .O(N240)
  );
  LUT6 #(
    .INIT ( 64'h0EEEEEEEEEEEEEEE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT331  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_311_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_313_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [40]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [41]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [39]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [38]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT33_5584 )
  );
  LUT5 #(
    .INIT ( 32'hFEFAFCF0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT332  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_7_4975 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [49]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT33_5584 ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<24>2 ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<24>1 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT332_5585 )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFEFFFFFFFC ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT28_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [44]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_306_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_301_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_311_o ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<29>2 ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<24>2 ),
    .O(N246)
  );
  LUT3 #(
    .INIT ( 8'hFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT321  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [38]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [39]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [41]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT32 )
  );
  LUT6 #(
    .INIT ( 64'hAFAFAFA8AAAAAAA8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT322  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [40]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_314_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_311_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_313_o ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT32 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT321_5589 )
  );
  LUT6 #(
    .INIT ( 64'hFEEEFCCCFAAAF000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT81  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_0_4955 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [26]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_304_o<7>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_315_o<7>1 ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<40>2 ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<40>1 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT8 )
  );
  LUT6 #(
    .INIT ( 64'hFEEEFCCCFAAAF000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT161  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_7_4961 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [33]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_304_o<7>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_315_o<7>1 ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<40>2 ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<40>1 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT16 )
  );
  LUT6 #(
    .INIT ( 64'hFEEEFCCCFAAAF000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT151  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_6_4960 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [32]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_304_o<7>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_315_o<7>1 ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<40>2 ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<40>1 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT15 )
  );
  LUT6 #(
    .INIT ( 64'hFEEEFCCCFAAAF000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT141  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_5_4959 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [31]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_304_o<7>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_315_o<7>1 ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<40>2 ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<40>1 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT14 )
  );
  LUT6 #(
    .INIT ( 64'hFEEEFCCCFAAAF000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT131  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_4_4958 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [30]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_304_o<7>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_315_o<7>1 ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<40>2 ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<40>1 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT13 )
  );
  LUT6 #(
    .INIT ( 64'hFEEEFCCCFAAAF000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT111  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_3_4957 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [29]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_304_o<7>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_315_o<7>1 ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<40>2 ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<40>1 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT11 )
  );
  LUT2 #(
    .INIT ( 4'h7 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT60_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [65]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4675 )
,
    .O(N250)
  );
  LUT6 #(
    .INIT ( 64'h0302333303003333 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT60  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_7_4996 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_309_o ),
    .I4(N250),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<7>2 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<63> )
  );
  LUT2 #(
    .INIT ( 4'h7 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT59_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [64]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4675 )
,
    .O(N252)
  );
  LUT6 #(
    .INIT ( 64'h0302333303003333 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT59  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_6_4995 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_309_o ),
    .I4(N252),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<7>2 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<62> )
  );
  LUT2 #(
    .INIT ( 4'h7 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT58_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [63]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4675 )
,
    .O(N254)
  );
  LUT6 #(
    .INIT ( 64'h0302333303003333 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT58  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_5_4994 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_309_o ),
    .I4(N254),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<7>2 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<61> )
  );
  LUT2 #(
    .INIT ( 4'h7 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT57_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [62]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4675 )
,
    .O(N256)
  );
  LUT6 #(
    .INIT ( 64'h0302333303003333 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT57  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_4_4993 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_309_o ),
    .I4(N256),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<7>2 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<60> )
  );
  LUT2 #(
    .INIT ( 4'h7 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT55_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [61]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4675 )
,
    .O(N258)
  );
  LUT6 #(
    .INIT ( 64'h0302333303003333 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT55  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_3_4992 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_309_o ),
    .I4(N258),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<7>2 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<59> )
  );
  LUT6 #(
    .INIT ( 64'h0F0E0F0A0F0C0F00 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT511  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_7_4989 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [65]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_308_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_309_o ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<10>1 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT51 )
  );
  LUT4 #(
    .INIT ( 16'h3320 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT512  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [57]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4675 )
,
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT51 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<55> )
  );
  LUT6 #(
    .INIT ( 64'h0F0E0F0A0F0C0F00 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT501  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_6_4988 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [64]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_308_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_309_o ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<10>1 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT50 )
  );
  LUT4 #(
    .INIT ( 16'h3320 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT502  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [56]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4675 )
,
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT50 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<54> )
  );
  LUT6 #(
    .INIT ( 64'h0F0E0F0A0F0C0F00 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT491  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_5_4987 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [63]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_308_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_309_o ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<10>1 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT49 )
  );
  LUT4 #(
    .INIT ( 16'h3320 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT492  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [55]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4675 )
,
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT49 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<53> )
  );
  LUT6 #(
    .INIT ( 64'h0F0E0F0A0F0C0F00 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT481  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_4_4986 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [62]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_308_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_309_o ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<10>1 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT48 )
  );
  LUT4 #(
    .INIT ( 16'h3320 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT482  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [54]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4675 )
,
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT48 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<52> )
  );
  LUT6 #(
    .INIT ( 64'h0F0E0F0A0F0C0F00 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT471  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_3_4985 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [61]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_308_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_309_o ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<10>1 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT47 )
  );
  LUT4 #(
    .INIT ( 16'h3320 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT472  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [53]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4675 )
,
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT47 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<51> )
  );
  LUT6 #(
    .INIT ( 64'h0F0E0F0A0F0C0F00 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT431  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_0_4983 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [58]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_308_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_309_o ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<10>1 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT43 )
  );
  LUT4 #(
    .INIT ( 16'h3320 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT432  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [50]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4675 )
,
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT43 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<48> )
  );
  LUT6 #(
    .INIT ( 64'h5555555455555555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_ctrl_out[7]_GND_30_o_mux_323_OUT6  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<29>2 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_302_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_301_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_315_o ),
    .I5(N262),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out[7]_GND_30_o_mux_323_OUT<5> )
  );
  LUT6 #(
    .INIT ( 64'h5555555455555555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_ctrl_out[7]_GND_30_o_mux_323_OUT3  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_302_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_303_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_301_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_311_o ),
    .I5(N264),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out[7]_GND_30_o_mux_323_OUT<2> )
  );
  LUT3 #(
    .INIT ( 8'h01 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_ctrl_out[7]_GND_30_o_mux_323_OUT7_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_306_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_307_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_308_o ),
    .O(N268)
  );
  LUT6 #(
    .INIT ( 64'h5555555455555555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_ctrl_out[7]_GND_30_o_mux_323_OUT7  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<29>2 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_302_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_301_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_315_o ),
    .I5(N268),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out[7]_GND_30_o_mux_323_OUT<6> )
  );
  LUT5 #(
    .INIT ( 32'h00000800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c3[6]_mux_228_OUT6_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_GND_30_o_equal_64_o<6>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [32]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [34]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [35]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [33]),
    .O(N272)
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFFFFFFD ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c3[6]_mux_228_OUT6  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_69_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_67_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_66_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_GND_30_o_equal_63_o ),
    .I5(N272),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c3[6]_mux_228_OUT<5> )
  );
  LUT5 #(
    .INIT ( 32'h00000800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c2[6]_mux_217_OUT6_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_GND_30_o_equal_54_o<6>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [25]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [27]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [28]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [26]),
    .O(N276)
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFFFFFFD ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c2[6]_mux_217_OUT6  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_PWR_32_o_equal_59_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_PWR_32_o_equal_56_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_PWR_32_o_equal_57_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_GND_30_o_equal_53_o ),
    .I5(N276),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c2[6]_mux_217_OUT<5> )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFFFFFFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control<2>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_PWR_32_o_equal_59_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_PWR_32_o_equal_56_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_PWR_32_o_equal_58_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_PWR_32_o_equal_57_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_GND_30_o_equal_53_o ),
    .I5(N278),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [2])
  );
  LUT5 #(
    .INIT ( 32'h00000800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c1[6]_mux_206_OUT6_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_GND_30_o_equal_44_o<6>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [18]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [20]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [21]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [19]),
    .O(N280)
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFFFFFFD ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c1[6]_mux_206_OUT6  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_PWR_32_o_equal_49_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_PWR_32_o_equal_46_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_PWR_32_o_equal_47_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_GND_30_o_equal_43_o ),
    .I5(N280),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c1[6]_mux_206_OUT<5> )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFFFFFFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control<1>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_PWR_32_o_equal_46_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_PWR_32_o_equal_47_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_PWR_32_o_equal_48_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_PWR_32_o_equal_49_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_GND_30_o_equal_43_o ),
    .I5(N282),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [1])
  );
  LUT5 #(
    .INIT ( 32'h00000800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c0[6]_mux_195_OUT6_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_GND_30_o_equal_34_o<6>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [11]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [13]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [14]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [12]),
    .O(N284)
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFFFFFFD ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c0[6]_mux_195_OUT6  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_PWR_32_o_equal_39_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_PWR_32_o_equal_36_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_PWR_32_o_equal_37_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_GND_30_o_equal_33_o ),
    .I5(N284),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c0[6]_mux_195_OUT<5> )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFFFFFFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control<0>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_PWR_32_o_equal_37_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_PWR_32_o_equal_36_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_PWR_32_o_equal_38_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_PWR_32_o_equal_39_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_GND_30_o_equal_33_o ),
    .I5(N286),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [0])
  );
  LUT5 #(
    .INIT ( 32'h00000800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c7[6]_mux_272_OUT6_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_GND_30_o_equal_104_o<6>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [60]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [62]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [63]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [61]),
    .O(N290)
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFFFFFFD ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c7[6]_mux_272_OUT6  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [7]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_PWR_32_o_equal_109_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_PWR_32_o_equal_106_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_PWR_32_o_equal_107_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_GND_30_o_equal_103_o ),
    .I5(N290),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c7[6]_mux_272_OUT<5> )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFFFFFFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control<7>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_PWR_32_o_equal_107_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_PWR_32_o_equal_106_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_PWR_32_o_equal_108_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_PWR_32_o_equal_109_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_GND_30_o_equal_103_o ),
    .I5(N292),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [7])
  );
  LUT5 #(
    .INIT ( 32'h00000800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c6[6]_mux_261_OUT6_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_GND_30_o_equal_94_o<6>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [53]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [55]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [56]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [54]),
    .O(N294)
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFFFFFFD ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c6[6]_mux_261_OUT6  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [6]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_PWR_32_o_equal_99_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_PWR_32_o_equal_96_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_PWR_32_o_equal_97_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_GND_30_o_equal_93_o ),
    .I5(N294),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c6[6]_mux_261_OUT<5> )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFFFFFFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control<6>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_PWR_32_o_equal_97_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_PWR_32_o_equal_96_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_PWR_32_o_equal_98_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_GND_30_o_equal_93_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_PWR_32_o_equal_99_o ),
    .I5(N296),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [6])
  );
  LUT5 #(
    .INIT ( 32'h00000800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c5[6]_mux_250_OUT6_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_GND_30_o_equal_84_o<6>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [46]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [48]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [49]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [47]),
    .O(N298)
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFFFFFFD ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c5[6]_mux_250_OUT6  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [5]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_PWR_32_o_equal_89_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_PWR_32_o_equal_86_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_PWR_32_o_equal_87_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_GND_30_o_equal_83_o ),
    .I5(N298),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c5[6]_mux_250_OUT<5> )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFFFFFFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control<5>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_PWR_32_o_equal_87_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_PWR_32_o_equal_86_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_PWR_32_o_equal_88_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_PWR_32_o_equal_89_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_GND_30_o_equal_83_o ),
    .I5(N300),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [5])
  );
  LUT3 #(
    .INIT ( 8'hF7 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_313_o<7>_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [8]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [6]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [5]),
    .O(N302)
  );
  LUT6 #(
    .INIT ( 64'h0000000000000200 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_313_o<7>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [7]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [9]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [4]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [3]),
    .I5(N302),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_313_o )
  );
  LUT3 #(
    .INIT ( 8'hFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_302_o<7>_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [8]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [6]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [5]),
    .O(N304)
  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_302_o<7>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [4]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [7]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [9]),
    .I5(N304),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_302_o )
  );
  LUT3 #(
    .INIT ( 8'hBF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_301_o<7>_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [8]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [6]),
    .O(N306)
  );
  LUT6 #(
    .INIT ( 64'h0000000001000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_301_o<7>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [7]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [9]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [4]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [3]),
    .I5(N306),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_301_o )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFBFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_valid_control[7]_AND_124_o_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [9]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [7]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [3]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [4]),
    .O(N308)
  );
  LUT6 #(
    .INIT ( 64'h0000000000000008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_303_o<7>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [9]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [7]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [4]),
    .I5(N306),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_303_o )
  );
  LUT6 #(
    .INIT ( 64'h0000000000008001 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_o4[3]_AND_120_o2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [40]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [38]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [39]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [41]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [3]),
    .I5(N320),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_o4[3]_AND_120_o2_4709 )
  );
  LUT6 #(
    .INIT ( 64'hEFEFEFECEFEFEFEF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT624  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [9]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT621 ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT622_5634 )
,
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/n0275 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<7> )
  );
  LUT6 #(
    .INIT ( 64'hFAF7FFF7BF5FBFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c6[6]_mux_261_OUT4_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [55]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_PWR_32_o_equal_96_o<6>1 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [54]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [56]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_GND_30_o_equal_94_o<6>1 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [53]),
    .O(N324)
  );
  LUT4 #(
    .INIT ( 16'hFFBF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c6[6]_mux_261_OUT4  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_PWR_32_o_equal_98_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [6]),
    .I2(N324),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_GND_30_o_equal_93_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c6[6]_mux_261_OUT<3> )
  );
  LUT6 #(
    .INIT ( 64'hFAF7FFF7BF5FBFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c5[6]_mux_250_OUT4_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [48]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_PWR_32_o_equal_86_o<6>1 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [47]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [49]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_GND_30_o_equal_84_o<6>1 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [46]),
    .O(N326)
  );
  LUT4 #(
    .INIT ( 16'hFFBF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c5[6]_mux_250_OUT4  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_PWR_32_o_equal_88_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [5]),
    .I2(N326),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_GND_30_o_equal_83_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c5[6]_mux_250_OUT<3> )
  );
  LUT6 #(
    .INIT ( 64'hFAF7FFF7BF5FBFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c7[6]_mux_272_OUT4_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [62]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_PWR_32_o_equal_106_o<6>1 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [61]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [63]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_GND_30_o_equal_104_o<6>1 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [60]),
    .O(N328)
  );
  LUT4 #(
    .INIT ( 16'hFFBF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c7[6]_mux_272_OUT4  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_PWR_32_o_equal_108_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [7]),
    .I2(N328),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_GND_30_o_equal_103_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c7[6]_mux_272_OUT<3> )
  );
  LUT6 #(
    .INIT ( 64'hFAF7FFF7BF5FBFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c3[6]_mux_228_OUT4_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [34]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_66_o<6>1 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [33]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [35]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_GND_30_o_equal_64_o<6>1 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [32]),
    .O(N330)
  );
  LUT6 #(
    .INIT ( 64'hFAF7FFF7BF5FBFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c2[6]_mux_217_OUT4_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [27]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_PWR_32_o_equal_56_o<6>1 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [26]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [28]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_GND_30_o_equal_54_o<6>1 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [25]),
    .O(N332)
  );
  LUT4 #(
    .INIT ( 16'hFFBF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c2[6]_mux_217_OUT4  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_PWR_32_o_equal_58_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [2]),
    .I2(N332),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_GND_30_o_equal_53_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c2[6]_mux_217_OUT<3> )
  );
  LUT5 #(
    .INIT ( 32'h02000080 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c4[6]_mux_239_OUT41  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_GND_30_o_equal_75_o<6>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [41]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [44]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [43]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [42]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c4[6]_mux_239_OUT4 )
  );
  LUT5 #(
    .INIT ( 32'h02000080 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c4[6]_mux_239_OUT42  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_PWR_32_o_equal_77_o<6>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [38]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [42]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [43]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [39]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c4[6]_mux_239_OUT41_5641 )
  );
  LUT5 #(
    .INIT ( 32'hFFFFFFFD ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c4[6]_mux_239_OUT43  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [4]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_GND_30_o_equal_74_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c4[6]_mux_239_OUT4 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c4[6]_mux_239_OUT41_5641 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_GND_30_o_equal_73_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c4[6]_mux_239_OUT<3> )
  );
  LUT6 #(
    .INIT ( 64'hFAF7FFF7BF5FBFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c0[6]_mux_195_OUT4_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [13]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_PWR_32_o_equal_36_o<6>1 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [12]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [14]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_GND_30_o_equal_34_o<6>1 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [11]),
    .O(N334)
  );
  LUT4 #(
    .INIT ( 16'hFFBF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c0[6]_mux_195_OUT4  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_PWR_32_o_equal_38_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [0]),
    .I2(N334),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_GND_30_o_equal_33_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c0[6]_mux_195_OUT<3> )
  );
  LUT6 #(
    .INIT ( 64'hFAF7FFF7BF5FBFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c1[6]_mux_206_OUT4_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [20]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_PWR_32_o_equal_46_o<6>1 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [19]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [21]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_GND_30_o_equal_44_o<6>1 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [18]),
    .O(N336)
  );
  LUT4 #(
    .INIT ( 16'hFFBF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c1[6]_mux_206_OUT4  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_PWR_32_o_equal_48_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [1]),
    .I2(N336),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_GND_30_o_equal_43_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c1[6]_mux_206_OUT<3> )
  );
  LUT6 #(
    .INIT ( 64'hEEAAFEBAEEAAFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_GND_30_o_mux_178_OUT312  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [9]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [8]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [4]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [6]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_GND_30_o_mux_178_OUT312_5644 )
  );
  LUT6 #(
    .INIT ( 64'h4440404000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o5  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [8]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [4]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o2_5646 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o3_5647 )
,
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o4_5648 )
,
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o31 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o5_5649 )
  );
  LUT6 #(
    .INIT ( 64'h8000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o6  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [6]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [7]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [4]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [5]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [2]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [3]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o6_5650 )
  );
  LUT6 #(
    .INIT ( 64'hFFA8FFA0FF00FF00 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o10  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o7_5651 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o9_5653 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o8_5652 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o6_5650 )
,
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [6]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [7]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o10_5654 )
  );
  LUT6 #(
    .INIT ( 64'h2323232323232320 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT56  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [7]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_302_o ),
    .I4(N338),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT5611 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<5> )
  );
  LUT3 #(
    .INIT ( 8'hEC ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT52_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [58]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4675 )
,
    .O(N344)
  );
  LUT6 #(
    .INIT ( 64'hFF32FF30FF33FF33 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT52  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c7_0_4990 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_309_o ),
    .I3(N344),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<7>2 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/n0275 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<56> )
  );
  LUT6 #(
    .INIT ( 64'h2323030322230003 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT46  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [52]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ),
    .I3(N346),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4675 )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<7>2 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<50> )
  );
  LUT4 #(
    .INIT ( 16'h3320 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT442  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [51]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4675 )
,
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT44 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<49> )
  );
  LUT5 #(
    .INIT ( 32'hFEFAFCF0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT171  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_0_4962 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [34]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_305_o ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<39>2 ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<39>3 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT17 )
  );
  LUT6 #(
    .INIT ( 64'hEFCFEECCEFCFEFCF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT172  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [26]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT111_4674 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT17 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/n0275 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<24> )
  );
  LUT6 #(
    .INIT ( 64'h0000000000001000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_118_o1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [9]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [8]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [6]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_GND_30_o_equal_93_o ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_GND_30_o_equal_103_o ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_118_o2_5664 )

  );
  LUT5 #(
    .INIT ( 32'h00000001 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_118_o2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_GND_30_o_equal_63_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_GND_30_o_equal_83_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_GND_30_o_equal_53_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_GND_30_o_equal_43_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_GND_30_o_equal_33_o ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_118_o3_5665 )

  );
  LUT4 #(
    .INIT ( 16'h1001 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2-In_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5069 ),
    .O(N362)
  );
  LUT6 #(
    .INIT ( 64'h44444444444444E4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2-In  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2_5068 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_806_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/q_543 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I5(N362),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2-In_5071 )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFFFFFFD ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd1-In_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next_reg [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/q_543 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [2]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .O(N364)
  );
  LUT6 #(
    .INIT ( 64'h00FF80FF00008000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd1-In  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5069 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ),
    .I4(N364),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd1_5067 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd1-In_5070 )
  );
  LUT6 #(
    .INIT ( 64'hA2A2A2A2A2FFA2A2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3-In1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2_5068 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5069 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3-In1_5668 )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFAAA28880 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3-In2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5069 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3-In1_5668 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3-In2_5669 )
  );
  LUT6 #(
    .INIT ( 64'h00200020FFFF0020 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3-In3  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3-In2_5669 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_806_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/q_543 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5069 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3-In )
  );
  LUT6 #(
    .INIT ( 64'h1455145514553655 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_next_state11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd1_5067 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2_5068 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5069 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next_reg [2]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next_reg [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_next_state1 )
  );
  LUT3 #(
    .INIT ( 8'h20 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_next_state12  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_next_state1 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/next_state [0])
  );
  LUT5 #(
    .INIT ( 32'h08080888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1631  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5069 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next_reg [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT163 )
  );
  LUT6 #(
    .INIT ( 64'h1414FFFF14144404 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1632  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2_5068 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5069 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd1_5067 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT163 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1631_5672 )
  );
  LUT4 #(
    .INIT ( 16'h0008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1633  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1631_5672 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out [8]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_6_4223 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data[63]_GND_31_o_mux_41_OUT<8> )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFEFEFEFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/next_state [2]),
    .I1(N366),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2_5068 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5069 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_6_4223 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT<0> )
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_glue_set_5674 ),
    .R(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 )
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int_0  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int_0_glue_set_5675 ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/_n0079 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [0])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int_6  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int_6_glue_set_5676 ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/_n0079 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [6])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_1  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_1_glue_set_5677 ),
    .R(rxreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_1_3392 )
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_3  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_3_glue_set_5678 ),
    .R(rxreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_3_3393 )
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_2  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_2_glue_set_5679 ),
    .R(rxreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_2_3394 )
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_1  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_1_glue_set_5680 ),
    .R(rxreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_1_3412 )
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_3  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_3_glue_set_5681 ),
    .R(rxreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_3_3413 )
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_2  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_2_glue_set_5682 ),
    .R(rxreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_2_3414 )
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_1  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_1_glue_set_5683 ),
    .R(rxreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_1_3432 )
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_3  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_3_glue_set_5684 ),
    .R(rxreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_3_3433 )
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_2  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_2_glue_set_5685 ),
    .R(rxreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_2_3434 )
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_7  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_7_glue_set_5686 ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n0856 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field [7])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_6  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_6_glue_set_5687 ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n0856 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field [6])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_5  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_5_glue_set_5688 ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n0856 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field [5])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_4  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_4_glue_set_5689 ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n0856 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field [4])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_3  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_3_glue_set_5690 ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n0856 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field [3])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_2  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_2_glue_set_5691 ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n0856 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field [2])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_1  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_1_glue_set_5692 ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n0856 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field [1])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_0  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_0_glue_set_5693 ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n0856 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field [0])
  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<14>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [14]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<14>_rt_5694 )

  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<13>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [13]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<13>_rt_5695 )

  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<12>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [12]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<12>_rt_5696 )

  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<11>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [11]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<11>_rt_5697 )

  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<10>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [10]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<10>_rt_5698 )

  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<9>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [9]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<9>_rt_5699 )

  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<8>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [8]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<8>_rt_5700 )

  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<7>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [7]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<7>_rt_5701 )

  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<6>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [6]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<6>_rt_5702 )

  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<5>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [5]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<5>_rt_5703 )

  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<4>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [4]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<4>_rt_5704 )

  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<3>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<3>_rt_5705 )

  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<2>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<2>_rt_5706 )

  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<1>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_cy<1>_rt_5707 )

  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<14>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [14]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<14>_rt_5708 )

  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<13>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [13]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<13>_rt_5709 )

  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<12>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [12]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<12>_rt_5710 )

  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<11>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [11]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<11>_rt_5711 )

  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<10>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [10]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<10>_rt_5712 )

  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<9>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [9]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<9>_rt_5713 )

  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<8>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [8]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<8>_rt_5714 )

  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<7>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [7]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<7>_rt_5715 )

  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<6>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [6]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<6>_rt_5716 )

  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<5>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [5]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<5>_rt_5717 )

  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<4>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [4]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<4>_rt_5718 )

  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<3>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<3>_rt_5719 )

  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<2>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<2>_rt_5720 )

  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<1>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_cy<1>_rt_5721 )

  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<14>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [14]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<14>_rt_5722 )

  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<13>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [13]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<13>_rt_5723 )

  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<12>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [12]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<12>_rt_5724 )

  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<11>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [11]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<11>_rt_5725 )

  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<10>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [10]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<10>_rt_5726 )

  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<9>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [9]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<9>_rt_5727 )

  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<8>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [8]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<8>_rt_5728 )

  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<7>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [7]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<7>_rt_5729 )

  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<6>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [6]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<6>_rt_5730 )

  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<5>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [5]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<5>_rt_5731 )

  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<4>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [4]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<4>_rt_5732 )

  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<3>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<3>_rt_5733 )

  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<2>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<2>_rt_5734 )

  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<1>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_cy<1>_rt_5735 )

  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<14>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [14]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<14>_rt_5736 )
  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<13>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [13]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<13>_rt_5737 )
  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<12>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [12]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<12>_rt_5738 )
  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<11>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [11]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<11>_rt_5739 )
  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<10>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [10]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<10>_rt_5740 )
  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<9>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [9]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<9>_rt_5741 )
  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<8>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [8]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<8>_rt_5742 )
  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<7>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [7]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<7>_rt_5743 )
  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<6>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [6]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<6>_rt_5744 )
  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<5>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [5]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<5>_rt_5745 )
  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<4>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [4]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<4>_rt_5746 )
  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<3>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<3>_rt_5747 )
  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<2>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<2>_rt_5748 )
  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<1>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_cy<1>_rt_5749 )
  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<6>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [6]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<6>_rt_5750 )
  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<5>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [5]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<5>_rt_5751 )
  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<4>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [4]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<4>_rt_5752 )
  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<3>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [3]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<3>_rt_5753 )
  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<2>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<2>_rt_5754 )
  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<1>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_cy<1>_rt_5755 )
  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<0>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [0]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_cy<0>_rt_5756 )

  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_xor<15>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [15]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_xor<15>_rt_5757 )

  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_xor<15>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [15]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_xor<15>_rt_5758 )

  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_xor<15>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [15]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_xor<15>_rt_5759 )

  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_xor<15>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [15]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_xor<15>_rt_5760 )
  );
  LUT1 #(
    .INIT ( 2'h2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_xor<7>_rt  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [7]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_xor<7>_rt_5761 )
  );
  FDR #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_10_0/q_0  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_5/d2_550 ),
    .R
(\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15/q_0 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_10_0/q_0_1959 )
  );
  FDR #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_14/q_0  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_14/q_0_rstpot_5762 ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_14/_n0014 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_14/q_0_1952 )
  );
  FDR #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_15/q_0  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_15/q_0_rstpot_5763 ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_14/_n0014 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_15/q_0_1953 )
  );
  FDR #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15/q_0  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15/q_0_rstpot_5764 ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_reset_clear_core_int ),
    .Q
(\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15/q_0 )
  );
  FDR #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_rstpot_5765 ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_reset_clear_core_int ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 )
  );
  FDR #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_9_0/q_0  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_9_0/q_0_rstpot_5766 ),
    .R
(\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15/q_0 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_4/d )
  );
  FDS   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/empty_int  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/empty_int_rstpot_5767 ),
    .S(txreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/empty_int_2366 )
  );
  FDS   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_rstpot_5768 ),
    .S(reset),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 )
  );
  FDR #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/full_int  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/full_int_rstpot_5769 ),
    .R(rxreset322),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/full_int_3072 )
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/b_lock  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/b_lock_rstpot_5770 ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/rxreset_signal_ok_OR_194_o ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_806_o )
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/hiber  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/hiber_rstpot_5771 ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4227 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o )
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_slip  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_slip_rstpot_5772 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_slip_261 )
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_rx_link_up_core_reg  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_rx_link_up_core_reg_rstpot_5773 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[2].synch_inst/d1_d_MUX_806_o )
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_we_rising  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_we_rising_rstpot_5774 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_we_rising_1339 )
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_rstpot_5775 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1341 )
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/indirect_read  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/indirect_read_rstpot_5776 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/indirect_read_1676 )
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/read_enable  (
    .C(txusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/read_enable_rstpot_5777 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/read_enable_2252 )
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd2  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd2_rstpot_5778 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd2_3333 )
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd1  (
    .C(clk156),
    .D
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd1_rstpot_5779 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd1_3334 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/newedge  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/newedge_rstpot_5780 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/newedge_3380 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/newedge  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/newedge_rstpot_5781 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/newedge_3384 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/newedge  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/newedge_rstpot_5782 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/newedge_3388 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/newedge  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/newedge_rstpot_5783 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/newedge_3400 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/newedge  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/newedge_rstpot_5784 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/newedge_3404 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/newedge  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/newedge_rstpot_5785 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/newedge_3408 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/newedge  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/newedge_rstpot_5786 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/newedge_3420 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/newedge  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/newedge_rstpot_5787 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/newedge_3424 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/newedge  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/newedge_rstpot_5788 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/newedge_3428 )
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/o4_0  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/o4_0_rstpot_5789 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/o4 [0])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/o0_0  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/o0_0_rstpot_5790 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/o0 [0])
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/local_fault  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/local_fault_rstpot_5791 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/local_fault_3335 )
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_sync_extra  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_sync_extra_rstpot_5792 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_sync_extra_3395 )
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_sync_extra  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_sync_extra_rstpot_5793 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_sync_extra_3415 )
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_sync_extra  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_sync_extra_rstpot_5794 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_sync_extra_3435 )
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/ignore_next_mismatch  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/ignore_next_mismatch_rstpot_5795 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/ignore_next_mismatch_4671 )
  );
  FD   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/we  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/we_rstpot1_5796 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/we_1362 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_8_11/q_0  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_8_11/q_0_rstpot1_5797 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_8_11/q_0_1927 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_8_10/q_0  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_8_10/q_0_rstpot1_5798 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_8_10/q_0_1926 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_1_2/q_0  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_1_2/q_0_rstpot1_5799 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_1_2/q_0_1960 )
  );
  FD #(
    .INIT ( 1'b0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_1_2/q_0  (
    .C(clk156),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_1_2/q_0_rstpot1_5800 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_1_2/q_0_1957 )
  );
  LUT6 #(
    .INIT ( 64'h0660042002400000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control<3>_SW1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [33]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [32]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [34]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [35]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_66_o<6>1 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_GND_30_o_equal_64_o<6>1 ),
    .O(N370)
  );
  LUT5 #(
    .INIT ( 32'hFFFFFFFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control<3>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_GND_30_o_equal_62_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_69_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_68_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_GND_30_o_equal_63_o ),
    .I4(N370),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [3])
  );
  LUT6 #(
    .INIT ( 64'h0421000104200000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control<2>_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [26]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [25]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [27]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [28]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_GND_30_o_equal_54_o<6>1 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_GND_30_o_equal_52_o<6>1 ),
    .O(N278)
  );
  LUT6 #(
    .INIT ( 64'h1009000110080000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control<1>_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [19]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [20]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [18]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [21]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_GND_30_o_equal_44_o<6>1 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_GND_30_o_equal_42_o<6>1 ),
    .O(N282)
  );
  LUT6 #(
    .INIT ( 64'h0421000104200000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control<0>_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [12]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [14]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [13]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [11]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_GND_30_o_equal_34_o<6>1 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_GND_30_o_equal_32_o<6>1 ),
    .O(N286)
  );
  LUT6 #(
    .INIT ( 64'h1009000110080000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control<7>_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [63]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [60]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [61]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [62]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_GND_30_o_equal_104_o<6>1 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_GND_30_o_equal_102_o<6>1 ),
    .O(N292)
  );
  LUT6 #(
    .INIT ( 64'h0241024000010000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control<6>_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [53]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [54]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [55]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [56]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_GND_30_o_equal_92_o<6>1 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_GND_30_o_equal_94_o<6>1 ),
    .O(N296)
  );
  LUT6 #(
    .INIT ( 64'h0421042000010000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control<5>_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [47]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [46]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [48]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [49]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_GND_30_o_equal_82_o<6>1 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_GND_30_o_equal_84_o<6>1 ),
    .O(N300)
  );
  LUT6 #(
    .INIT ( 64'h9060090609069060 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_GND_30_o_equal_73_o<6>_SW1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [39]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [20]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [40]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [19]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [0]),
    .O(N372)
  );
  LUT6 #(
    .INIT ( 64'h0010000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_GND_30_o_equal_73_o<6>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [38]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [43]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [41]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [44]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [42]),
    .I5(N372),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_GND_30_o_equal_73_o )
  );
  LUT6 #(
    .INIT ( 64'h69FFFF69FF6969FF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_69_o<6>_SW1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [23]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [4]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [36]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [22]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [3]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [37]),
    .O(N374)
  );
  LUT6 #(
    .INIT ( 64'h0001000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_69_o<6>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [31]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [33]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [32]),
    .I3(N374),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [34]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [35]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_69_o )
  );
  LUT6 #(
    .INIT ( 64'h9600009600969600 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_68_o<6>_SW1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [36]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [23]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [4]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [37]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [3]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [22]),
    .O(N376)
  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_68_o<6>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [33]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [31]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [32]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [35]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [34]),
    .I5(N376),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_68_o )
  );
  LUT5 #(
    .INIT ( 32'hF6F4F6F6 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_r_type_next_reg[2]_GND_30_o_mux_182_OUT3_SW0_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_o4[3]_AND_120_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_GND_30_o_mux_178_OUT31 ),
    .O(N381)
  );
  LUT3 #(
    .INIT ( 8'hBE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_r_type_next_reg[2]_GND_30_o_mux_182_OUT3_SW0_SW1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [0]),
    .O(N382)
  );
  LUT5 #(
    .INIT ( 32'hFFFFFDFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o211_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [4]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [7]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [5]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_GND_30_o_equal_73_o ),
    .O(N384)
  );
  LUT6 #(
    .INIT ( 64'h4000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_118_o3  (
    .I0(N384),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_118_o2_5664 )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_118_o3_5665 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [4]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o31 ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_118_o1_4700 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_118_o )
  );
  LUT6 #(
    .INIT ( 64'h0096000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o4  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [57]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [38]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [7]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [3]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o4_5648 )
  );
  LUT5 #(
    .INIT ( 32'h00000069 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_GND_30_o_equal_102_o<6>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [26]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [65]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [7]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [64]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [59]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_GND_30_o_equal_102_o<6>1 )
  );
  LUT5 #(
    .INIT ( 32'h00000069 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_GND_30_o_equal_92_o<6>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [58]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [19]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [57]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [52]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_GND_30_o_equal_92_o<6>1 )
  );
  LUT5 #(
    .INIT ( 32'h00000069 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_GND_30_o_equal_82_o<6>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [8]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [51]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [12]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [50]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [45]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_GND_30_o_equal_82_o<6>1 )
  );
  LUT5 #(
    .INIT ( 32'h00000069 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_GND_30_o_equal_52_o<6>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [10]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [30]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [29]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [29]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [24]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_GND_30_o_equal_52_o<6>1 )
  );
  LUT5 #(
    .INIT ( 32'h00000069 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_GND_30_o_equal_42_o<6>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [17]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [23]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [36]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [22]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [17]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_GND_30_o_equal_42_o<6>1 )
  );
  LUT5 #(
    .INIT ( 32'h00000069 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_GND_30_o_equal_32_o<6>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [24]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [43]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [16]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [15]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [10]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_GND_30_o_equal_32_o<6>1 )
  );
  LUT5 #(
    .INIT ( 32'h00000069 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_GND_30_o_equal_62_o<6>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [22]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [37]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [36]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [31]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_GND_30_o_equal_62_o<6>1 )
  );
  LUT5 #(
    .INIT ( 32'h00960000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_GND_30_o_equal_104_o<6>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [25]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [64]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [6]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [65]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [59]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_GND_30_o_equal_104_o<6>1 )
  );
  LUT5 #(
    .INIT ( 32'h00960000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_PWR_32_o_equal_106_o<6>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [26]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [65]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [7]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [64]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [59]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_PWR_32_o_equal_106_o<6>1 )
  );
  LUT5 #(
    .INIT ( 32'h00960000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_GND_30_o_equal_94_o<6>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [57]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [18]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [58]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [52]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_GND_30_o_equal_94_o<6>1 )
  );
  LUT5 #(
    .INIT ( 32'h00960000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_PWR_32_o_equal_96_o<6>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [58]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [19]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [57]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [52]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_PWR_32_o_equal_96_o<6>1 )
  );
  LUT5 #(
    .INIT ( 32'h00960000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_GND_30_o_equal_84_o<6>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [9]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [50]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [11]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [51]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [45]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_GND_30_o_equal_84_o<6>1 )
  );
  LUT5 #(
    .INIT ( 32'h00960000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_PWR_32_o_equal_86_o<6>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [8]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [51]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [12]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [50]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [45]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_PWR_32_o_equal_86_o<6>1 )
  );
  LUT5 #(
    .INIT ( 32'h00960000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_GND_30_o_equal_54_o<6>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [11]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [30]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [29]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [30]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [24]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_GND_30_o_equal_54_o<6>1 )
  );
  LUT5 #(
    .INIT ( 32'h00960000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_PWR_32_o_equal_56_o<6>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [10]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [30]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [29]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [29]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [24]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_PWR_32_o_equal_56_o<6>1 )
  );
  LUT5 #(
    .INIT ( 32'h00960000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_GND_30_o_equal_44_o<6>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [18]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [22]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [37]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [23]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [17]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_GND_30_o_equal_44_o<6>1 )
  );
  LUT5 #(
    .INIT ( 32'h00960000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_PWR_32_o_equal_46_o<6>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [17]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [23]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [36]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [22]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [17]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_PWR_32_o_equal_46_o<6>1 )
  );
  LUT5 #(
    .INIT ( 32'h00960000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_GND_30_o_equal_34_o<6>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [25]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [44]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [15]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [16]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [10]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_GND_30_o_equal_34_o<6>1 )
  );
  LUT5 #(
    .INIT ( 32'h00960000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_PWR_32_o_equal_36_o<6>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [24]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [43]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [16]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [15]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [10]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_PWR_32_o_equal_36_o<6>1 )
  );
  LUT5 #(
    .INIT ( 32'h00960000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_GND_30_o_equal_64_o<6>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [23]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [4]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [36]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [37]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [31]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_GND_30_o_equal_64_o<6>1 )
  );
  LUT5 #(
    .INIT ( 32'h00960000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_66_o<6>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [22]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [37]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [36]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [31]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_66_o<6>1 )
  );
  LUT5 #(
    .INIT ( 32'h00000069 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_GND_30_o_equal_72_o<6>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [40]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [19]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [39]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [38]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_GND_30_o_equal_72_o<6>1 )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFF55554044 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_7_glue_set  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT232 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[2]_AND_57_o )
,
    .I3(N160),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11322 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n0915 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_7_glue_set_5686 )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFFF1110 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_4_glue_set  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[1]_AND_52_o )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out232 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT141_5331 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT145_5333 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT14 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n0915 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_4_glue_set_5689 )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFAAA22A22 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_3_glue_set  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1162 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[2]_AND_57_o )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT112_5508 ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[31]_PWR_23_o_equal_118_o_mmx_out ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n0915 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_3_glue_set_5690 )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFF11105554 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_1_glue_set  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out232 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT54_5412 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT5 ),
    .I4(N390),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n0915 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_1_glue_set_5692 )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFF44405555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_5_glue_set  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1162 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT17 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT175 ),
    .I4(N394),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n0915 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_5_glue_set_5688 )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFAEEE0444 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT51  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[2]_AND_57_o )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[3]_AND_61_o )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_126_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out1411 ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[31]_PWR_23_o_equal_118_o_mmx_out ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[1]_AND_52_o )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT5 )
  );
  LUT6 #(
    .INIT ( 64'h8880080008000800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT113211  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out141 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[2] ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[15]_PWR_23_o_equal_102_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[1] ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/n0141 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11321 )
  );
  LUT5 #(
    .INIT ( 32'h0202FF02 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1171111  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[63]_PWR_23_o_equal_148_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [6]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11411 ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[5]_AND_66_o )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[55]_PWR_23_o_equal_142_o_mmx_out_3506 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT117111 )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFEEEBAAA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT82  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[2]_AND_57_o )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[4]_AND_64_o )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[5]_AND_66_o )
,
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[55]_PWR_23_o_equal_142_o_mmx_out_3506 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[47]_PWR_23_o_equal_134_o_mmx_out1 )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[3]_AND_61_o )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT81_5323 )
  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT171  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [24]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [25]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [27]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[31]_tx_xgmii_data_reg1[31]_OR_80_o2 )
,
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[7]_reduce_and_188_o ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[2]_AND_57_o )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT17 )
  );
  LUT6 #(
    .INIT ( 64'h88808880FFFF8880 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT22  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[3]_reduce_and_158_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1141 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_166_o ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_tx_xgmii_data_reg1[39]_OR_153_o_3588 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[5]_AND_66_o )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[55]_PWR_23_o_equal_142_o_mmx_out_3506 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT21 )
  );
  LUT6 #(
    .INIT ( 64'h11015545BBABFFEF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT23_SW0  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[3]_AND_61_o )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[4]_AND_64_o )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[5]_AND_66_o )
,
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[55]_PWR_23_o_equal_142_o_mmx_out_3506 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[47]_PWR_23_o_equal_134_o_mmx_out ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_126_o_mmx_out1 )
,
    .O(N160)
  );
  LUT6 #(
    .INIT ( 64'h1555555555555555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT111  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_reduce_and_78_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[2] ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out141 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[1] ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/n0141 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11 )
  );
  LUT5 #(
    .INIT ( 32'h7FFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[15]_PWR_23_o_equal_102_o1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[3] ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[4] ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out1411 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[15]_PWR_23_o_equal_102_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[2] ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[15]_PWR_23_o_equal_102_o_mmx_out )
  );
  LUT5 #(
    .INIT ( 32'h2A2A2AFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT83  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1141 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_166_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[3]_reduce_and_158_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11411 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [6]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT82_5324 )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFFFFFFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_ctrl_out[7]_GND_30_o_mux_323_OUT5_SW0_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_311_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_310_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_301_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_313_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_312_o ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .O(N400)
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFEFFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_ctrl_out[7]_GND_30_o_mux_323_OUT5  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_302_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_306_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_315_o ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<29>2 ),
    .I4(N400),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/n0275 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out[7]_GND_30_o_mux_323_OUT<4> )
  );
  LUT5 #(
    .INIT ( 32'hFFFFFFFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_ctrl_out[7]_GND_30_o_mux_323_OUT1_SW0_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_301_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_314_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_313_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_312_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .O(N402)
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFEFFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_ctrl_out[7]_GND_30_o_mux_323_OUT1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_310_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_302_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_311_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_315_o ),
    .I4(N402),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/n0275 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_ctrl_out[7]_GND_30_o_mux_323_OUT<0> )
  );
  LUT6 #(
    .INIT ( 64'hEFEFEFECEFEFEFEF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT23  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [4]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<48>2 ),
    .I4(N404),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/n0275 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<2> )
  );
  LUT6 #(
    .INIT ( 64'hDFFFFFFFFFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11113  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_tx_xgmii_data_reg1[39]_OR_153_o_3588 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_166_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[3] ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[2] ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[1] ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[0] ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11112_5336 )
  );
  LUT4 #(
    .INIT ( 16'hFF7F ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[55]_PWR_23_o_equal_142_o_mmx_out_SW0_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [51]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [50]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [48]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [49]),
    .O(N406)
  );
  LUT6 #(
    .INIT ( 64'hDFFFFFFFFFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[55]_PWR_23_o_equal_142_o_mmx_out  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[7] ),
    .I1(N406),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [55]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [54]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [53]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [52]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[55]_PWR_23_o_equal_142_o_mmx_out_3506 )

  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFF10080000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control<4>_SW1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [43]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [42]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [44]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [41]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_GND_30_o_equal_75_o<6>1 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_GND_30_o_equal_73_o ),
    .O(N408)
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFFFFFFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control<4>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_PWR_32_o_equal_79_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_GND_30_o_equal_72_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_PWR_32_o_equal_78_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_PWR_32_o_equal_77_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_GND_30_o_equal_74_o ),
    .I5(N408),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [4])
  );
  LUT4 #(
    .INIT ( 16'hFFF8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<39>31  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_304_o<7>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_315_o<7>1 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_303_o ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<48>2 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<39>3 )
  );
  LUT4 #(
    .INIT ( 16'h8000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out233  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out231 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_reduce_and_78_o )
  );
  LUT6 #(
    .INIT ( 64'h96FFFF96FF9696FF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_GND_30_o_equal_74_o<6>_SW1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [39]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [20]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [19]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [40]),
    .O(N410)
  );
  LUT6 #(
    .INIT ( 64'h0000000000000080 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_GND_30_o_equal_74_o<6>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [38]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [43]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [41]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [44]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [42]),
    .I5(N410),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_GND_30_o_equal_74_o )
  );
  LUT5 #(
    .INIT ( 32'h80000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out2311  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [7]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [4]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [5]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [6]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out231 )
  );
  LUT5 #(
    .INIT ( 32'h80000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out14115_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [6]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [7]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [58]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [50]),
    .O(N414)
  );
  LUT6 #(
    .INIT ( 64'h0080008000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out14115  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code82_5417 ),
    .I1(N414),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code72 ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o )
,
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out14114_5490 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out14112_5488 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out1411 )
  );
  LUT6 #(
    .INIT ( 64'h0400000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o211  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [7]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [4]),
    .I2(N416),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [5]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [7]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [6]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o21 )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFFFFFFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/out8  (
    .I0(N248),
    .I1(N418),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_308_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_313_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_309_o ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<10>1 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/n0275 )
  );
  LUT6 #(
    .INIT ( 64'hD7EB7DBEEBD7BE7D ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_GND_30_o_equal_103_o<6>1_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [62]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [65]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [26]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [4]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [7]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [23]),
    .O(N420)
  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_GND_30_o_equal_103_o<6>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [61]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [64]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [60]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [59]),
    .I4(N420),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [63]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_GND_30_o_equal_103_o )
  );
  LUT6 #(
    .INIT ( 64'h6F9FF6F9F6F96F9F ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_PWR_32_o_equal_107_o<6>1_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [61]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [22]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [65]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [26]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [7]),
    .O(N422)
  );
  LUT6 #(
    .INIT ( 64'h0000000000000200 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_PWR_32_o_equal_107_o<6>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [59]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [64]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [62]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [63]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [60]),
    .I5(N422),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_PWR_32_o_equal_107_o )
  );
  LUT6 #(
    .INIT ( 64'h8228411441148228 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_PWR_32_o_equal_106_o<6>2_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [62]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [26]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [65]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [7]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [4]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [23]),
    .O(N424)
  );
  LUT6 #(
    .INIT ( 64'h0004000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_PWR_32_o_equal_106_o<6>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [64]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [59]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [61]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [63]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [60]),
    .I5(N424),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_PWR_32_o_equal_106_o )
  );
  LUT6 #(
    .INIT ( 64'h69FFFF69FF6969FF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_PWR_32_o_equal_109_o<6>1_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [64]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [6]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [25]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [23]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [4]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [62]),
    .O(N426)
  );
  LUT6 #(
    .INIT ( 64'h0000000000000008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_PWR_32_o_equal_109_o<6>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [65]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [63]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [60]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [61]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [59]),
    .I5(N426),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_PWR_32_o_equal_109_o )
  );
  LUT6 #(
    .INIT ( 64'h9009600609900660 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_PWR_32_o_equal_108_o<6>2_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [60]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [21]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [64]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [6]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [2]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [25]),
    .O(N428)
  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_PWR_32_o_equal_108_o<6>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [65]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [63]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [61]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [59]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [62]),
    .I5(N428),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_PWR_32_o_equal_108_o )
  );
  LUT6 #(
    .INIT ( 64'hDE7B7BDEEDB7B7ED ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_GND_30_o_equal_93_o<6>1_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [55]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [58]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [4]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [19]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [16]),
    .O(N430)
  );
  LUT6 #(
    .INIT ( 64'h0000000010000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_GND_30_o_equal_93_o<6>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [52]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [57]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [53]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [54]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [56]),
    .I5(N430),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_GND_30_o_equal_93_o )
  );
  LUT6 #(
    .INIT ( 64'h69FFFF69FF6969FF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_PWR_32_o_equal_97_o<6>1_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [5]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [54]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [15]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [19]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [58]),
    .O(N432)
  );
  LUT6 #(
    .INIT ( 64'h0000000000020000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_PWR_32_o_equal_97_o<6>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [52]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [57]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [53]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [55]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [56]),
    .I5(N432),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_PWR_32_o_equal_97_o )
  );
  LUT6 #(
    .INIT ( 64'h8228411441148228 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_PWR_32_o_equal_96_o<6>2_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [55]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [19]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [58]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [4]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [16]),
    .O(N434)
  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_PWR_32_o_equal_96_o<6>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [52]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [57]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [53]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [56]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [54]),
    .I5(N434),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_PWR_32_o_equal_96_o )
  );
  LUT6 #(
    .INIT ( 64'h69FFFF69FF6969FF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_PWR_32_o_equal_99_o<6>1_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [55]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [4]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [16]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [18]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [57]),
    .O(N436)
  );
  LUT6 #(
    .INIT ( 64'h0001000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_PWR_32_o_equal_99_o<6>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [52]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [54]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [53]),
    .I3(N436),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [56]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [58]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_PWR_32_o_equal_99_o )
  );
  LUT6 #(
    .INIT ( 64'h8228411441148228 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_PWR_32_o_equal_98_o<6>2_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [6]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [18]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [57]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [53]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [14]),
    .O(N438)
  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_PWR_32_o_equal_98_o<6>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [58]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [52]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [54]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [56]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [55]),
    .I5(N438),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_PWR_32_o_equal_98_o )
  );
  LUT6 #(
    .INIT ( 64'h96FFFF96FF9696FF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_GND_30_o_equal_83_o<6>1_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [51]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [12]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [8]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [11]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [9]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [48]),
    .O(N440)
  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_GND_30_o_equal_83_o<6>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [47]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [50]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [46]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [45]),
    .I4(N440),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [49]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_GND_30_o_equal_83_o )
  );
  LUT6 #(
    .INIT ( 64'h69FFFF69FF6969FF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_PWR_32_o_equal_87_o<6>1_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [51]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [12]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [8]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [8]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [47]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [12]),
    .O(N442)
  );
  LUT6 #(
    .INIT ( 64'h0000000000020000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_PWR_32_o_equal_87_o<6>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [45]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [50]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [46]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [48]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [49]),
    .I5(N442),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_PWR_32_o_equal_87_o )
  );
  LUT6 #(
    .INIT ( 64'h8228411441148228 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_PWR_32_o_equal_86_o<6>2_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [48]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [8]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [12]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [51]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [9]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [11]),
    .O(N444)
  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_PWR_32_o_equal_86_o<6>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [45]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [50]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [46]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [49]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [47]),
    .I5(N444),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_PWR_32_o_equal_86_o )
  );
  LUT6 #(
    .INIT ( 64'h69FFFF69FF6969FF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_PWR_32_o_equal_89_o<6>1_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [50]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [11]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [9]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [11]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [9]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [48]),
    .O(N446)
  );
  LUT6 #(
    .INIT ( 64'h0001000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_PWR_32_o_equal_89_o<6>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [45]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [47]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [46]),
    .I3(N446),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [49]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [51]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_PWR_32_o_equal_89_o )
  );
  LUT6 #(
    .INIT ( 64'h9009099060060660 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_PWR_32_o_equal_88_o<6>2_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [46]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [13]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [9]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [50]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [11]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [7]),
    .O(N448)
  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_PWR_32_o_equal_88_o<6>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [51]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [45]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [47]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [49]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [48]),
    .I5(N448),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_PWR_32_o_equal_88_o )
  );
  LUT6 #(
    .INIT ( 64'h96FFFF96FF9696FF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_GND_30_o_equal_53_o<6>1_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [10]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [30]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [29]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [25]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [34]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [15]),
    .O(N450)
  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_GND_30_o_equal_53_o<6>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [27]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [29]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [26]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [24]),
    .I4(N450),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [28]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_GND_30_o_equal_53_o )
  );
  LUT6 #(
    .INIT ( 64'hF6F96F9F6F9FF6F9 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_PWR_32_o_equal_57_o<6>1_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [10]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [30]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [15]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [29]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [34]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [25]),
    .O(N452)
  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_PWR_32_o_equal_57_o<6>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [24]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [29]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [26]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [27]),
    .I4(N452),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [28]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_PWR_32_o_equal_57_o )
  );
  LUT6 #(
    .INIT ( 64'h69FFFF69FF6969FF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_PWR_32_o_equal_56_o<6>2_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [15]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [34]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [25]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [10]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [29]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [30]),
    .O(N454)
  );
  LUT6 #(
    .INIT ( 64'h0001000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_PWR_32_o_equal_56_o<6>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [29]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [28]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [26]),
    .I3(N454),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [24]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [27]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_PWR_32_o_equal_56_o )
  );
  LUT6 #(
    .INIT ( 64'hF6F96F9F6F9FF6F9 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_PWR_32_o_equal_59_o<6>1_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [30]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [29]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [15]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [11]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [34]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [25]),
    .O(N456)
  );
  LUT6 #(
    .INIT ( 64'h0000000002000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_PWR_32_o_equal_59_o<6>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [30]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [24]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [26]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [27]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [28]),
    .I5(N456),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_PWR_32_o_equal_59_o )
  );
  LUT6 #(
    .INIT ( 64'h8228411441148228 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_PWR_32_o_equal_58_o<6>2_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [15]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [11]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [30]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [29]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [34]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [25]),
    .O(N458)
  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_PWR_32_o_equal_58_o<6>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [30]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [24]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [26]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [28]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [27]),
    .I5(N458),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_PWR_32_o_equal_58_o )
  );
  LUT6 #(
    .INIT ( 64'hF66FF99F6FF69FF9 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_GND_30_o_equal_43_o<6>1_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [41]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [18]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [36]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [17]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [22]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [23]),
    .O(N460)
  );
  LUT6 #(
    .INIT ( 64'h0000000010000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_GND_30_o_equal_43_o<6>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [22]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [17]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [19]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [20]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [21]),
    .I5(N460),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_GND_30_o_equal_43_o )
  );
  LUT6 #(
    .INIT ( 64'h69FFFF69FF6969FF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_PWR_32_o_equal_47_o<6>1_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [40]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [21]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [19]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [17]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [36]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [23]),
    .O(N462)
  );
  LUT6 #(
    .INIT ( 64'h0000000000040000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_PWR_32_o_equal_47_o<6>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [22]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [17]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [20]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [18]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [21]),
    .I5(N462),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_PWR_32_o_equal_47_o )
  );
  LUT6 #(
    .INIT ( 64'h9FF96FF6F99FF66F ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_PWR_32_o_equal_46_o<6>2_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [40]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [21]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [17]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [36]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [19]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [23]),
    .O(N464)
  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_PWR_32_o_equal_46_o<6>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [17]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [22]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [20]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [21]),
    .I4(N464),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [18]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_PWR_32_o_equal_46_o )
  );
  LUT6 #(
    .INIT ( 64'hBEEB7DD77DD7BEEB ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_PWR_32_o_equal_49_o<6>1_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [41]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [18]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [22]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [37]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [18]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [22]),
    .O(N466)
  );
  LUT6 #(
    .INIT ( 64'h0000000002000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_PWR_32_o_equal_49_o<6>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [23]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [17]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [19]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [20]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [21]),
    .I5(N466),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_PWR_32_o_equal_49_o )
  );
  LUT6 #(
    .INIT ( 64'h7DD7BEEBBEEB7DD7 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_PWR_32_o_equal_48_o<6>2_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [41]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [18]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [22]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [37]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [18]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [22]),
    .O(N468)
  );
  LUT6 #(
    .INIT ( 64'h0000000000000020 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_PWR_32_o_equal_48_o<6>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [23]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [17]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [19]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [20]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [21]),
    .I5(N468),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_PWR_32_o_equal_48_o )
  );
  LUT6 #(
    .INIT ( 64'hFF6969FF69FFFF69 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_GND_30_o_equal_33_o<6>1_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [46]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [27]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [13]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [43]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [24]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [16]),
    .O(N470)
  );
  LUT6 #(
    .INIT ( 64'h0000000000400000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_GND_30_o_equal_33_o<6>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [15]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [12]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [14]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [10]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [11]),
    .I5(N470),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_GND_30_o_equal_33_o )
  );
  LUT6 #(
    .INIT ( 64'h9060090609069060 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_PWR_32_o_equal_37_o<6>1_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [47]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [28]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [43]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [12]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [24]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [16]),
    .O(N472)
  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_PWR_32_o_equal_37_o<6>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [10]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [15]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [14]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [13]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [11]),
    .I5(N472),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_PWR_32_o_equal_37_o )
  );
  LUT6 #(
    .INIT ( 64'h69FFFF69FF6969FF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_PWR_32_o_equal_36_o<6>2_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [27]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [46]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [13]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [24]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [43]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [16]),
    .O(N474)
  );
  LUT6 #(
    .INIT ( 64'h0001000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_PWR_32_o_equal_36_o<6>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [15]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [12]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [14]),
    .I3(N474),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [10]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [11]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_PWR_32_o_equal_36_o )
  );
  LUT6 #(
    .INIT ( 64'h8228411441148228 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_PWR_32_o_equal_39_o<6>1_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [27]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [25]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [44]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [15]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [46]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [13]),
    .O(N476)
  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_PWR_32_o_equal_39_o<6>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [16]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [10]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [14]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [12]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [11]),
    .I5(N476),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_PWR_32_o_equal_39_o )
  );
  LUT6 #(
    .INIT ( 64'h7DD7BEEBBEEB7DD7 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_PWR_32_o_equal_38_o<6>2_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [48]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [44]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [15]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [25]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [11]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [29]),
    .O(N478)
  );
  LUT6 #(
    .INIT ( 64'h0001000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_PWR_32_o_equal_38_o<6>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [10]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [13]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [14]),
    .I3(N478),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [16]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [12]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_PWR_32_o_equal_38_o )
  );
  LUT6 #(
    .INIT ( 64'hFF9696FF96FFFF96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_GND_30_o_equal_62_o<6>2_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [34]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [6]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [25]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [37]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [3]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [22]),
    .O(N480)
  );
  LUT6 #(
    .INIT ( 64'h0000000000000001 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_GND_30_o_equal_62_o<6>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [36]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [31]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [35]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [33]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [32]),
    .I5(N480),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_GND_30_o_equal_62_o )
  );
  LUT6 #(
    .INIT ( 64'hFF6969FF69FFFF69 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_GND_30_o_equal_63_o<6>1_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [34]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [6]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [25]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [37]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [3]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [22]),
    .O(N482)
  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_GND_30_o_equal_63_o<6>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [33]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [36]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [32]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [31]),
    .I4(N482),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [35]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_GND_30_o_equal_63_o )
  );
  LUT6 #(
    .INIT ( 64'hF99F9FF9F66F6FF6 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_GND_30_o_equal_72_o<6>2_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [43]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [16]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [40]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [19]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [4]),
    .O(N484)
  );
  LUT6 #(
    .INIT ( 64'h0000000000000001 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_GND_30_o_equal_72_o<6>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [39]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [38]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [44]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [42]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [41]),
    .I5(N484),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_GND_30_o_equal_72_o )
  );
  LUT6 #(
    .INIT ( 64'hF66FF99F6FF69FF9 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_PWR_32_o_equal_79_o<6>1_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [43]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [16]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [40]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [19]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [4]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [0]),
    .O(N486)
  );
  LUT6 #(
    .INIT ( 64'h0000000010000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_PWR_32_o_equal_79_o<6>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [38]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [39]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [41]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [44]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [42]),
    .I5(N486),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_PWR_32_o_equal_79_o )
  );
  LUT6 #(
    .INIT ( 64'hEFEFEFECEFEFEFEF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT30  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [38]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ),
    .I3(N488),
    .I4(N238),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/n0275 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<36> )
  );
  LUT6 #(
    .INIT ( 64'hEFEFEFECEFEFEFEF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT29  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [37]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ),
    .I3(N490),
    .I4(N240),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/n0275 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<35> )
  );
  LUT6 #(
    .INIT ( 64'hEFEFEFECEFEFEFEF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT333  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [41]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ),
    .I3(N492),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT332_5585 )
,
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/n0275 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<39> )
  );
  LUT5 #(
    .INIT ( 32'hFFFEFEFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<29>11_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_313_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_315_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_302_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_314_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [36]),
    .O(N494)
  );
  LUT6 #(
    .INIT ( 64'hEFEFEFECEFEFEFEF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT28  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [36]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ),
    .I3(N494),
    .I4(N246),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/n0275 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<34> )
  );
  LUT4 #(
    .INIT ( 16'hFFFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<29>11_SW1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_302_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_315_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_313_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_312_o ),
    .O(N496)
  );
  LUT6 #(
    .INIT ( 64'hEFEFEFECEFEFEFEF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT34  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [5]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ),
    .I3(N496),
    .I4(N312),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/n0275 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<3> )
  );
  LUT6 #(
    .INIT ( 64'hEFEFEFECEFEFEFEF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT45  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [6]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ),
    .I3(N496),
    .I4(N314),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/n0275 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<4> )
  );
  LUT6 #(
    .INIT ( 64'hCAAAAAAAAAAAAAAA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_GND_30_o_mux_178_OUT314  (
    .I0(N500),
    .I1(N501),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_GND_30_o_mux_178_OUT31 )
  );
  LUT6 #(
    .INIT ( 64'hEFF7EFF7EFF7FFF7 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control<3>_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [6]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [4]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [5]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_GND_30_o_equal_62_o ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_GND_30_o_equal_63_o ),
    .O(N503)
  );
  LUT6 #(
    .INIT ( 64'h222222202222222A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o1_5645 )
,
    .I1(N504),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_68_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_69_o ),
    .I4(N370),
    .I5(N503),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o2_5646 )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFF55551110 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11116_SW1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11111_5335 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT522 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[2]_AND_57_o )
,
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[3]_AND_61_o )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[1]_AND_52_o )
,
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out232 ),
    .O(N507)
  );
  LUT6 #(
    .INIT ( 64'h2222222200022022 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11117  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/n0153 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11114 ),
    .I3(N506),
    .I4(N507),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1111 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/PWR_23_o_GND_22_o_mux_218_OUT [2])
  );
  LUT6 #(
    .INIT ( 64'h555411105557DDDF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11115  (
    .I0(N514),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_GND_22_o_equal_165_o ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_PWR_23_o_equal_185_o_mmx_out1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_GND_22_o_equal_181_o ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_166_o_mmx_out2 )
,
    .I5(N513),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11114 )
  );
  LUT6 #(
    .INIT ( 64'h070007778F888FFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT113_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n09151_3483 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_PWR_23_o_equal_185_o2 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[47]_PWR_23_o_equal_134_o_mmx_out ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[4]_AND_64_o )
,
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT117111 ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_126_o_mmx_out1 )
,
    .O(N158)
  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT17111  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out141 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[23]_PWR_23_o_equal_110_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out231 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [2]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1711 )
  );
  LUT6 #(
    .INIT ( 64'h5555555544444440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT182  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [27]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<56>3 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_314_o ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT18 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<25> )
  );
  LUT6 #(
    .INIT ( 64'hEE0EAA0ACC0C0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT181  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_1_4963 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [35]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [0]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<39>2 ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<39>3 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT18 )
  );
  LUT6 #(
    .INIT ( 64'h9600000000000096 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [37]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [56]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/expected_data[63]_inv_8_OUT<0> ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [4]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<0> )

  );
  LUT6 #(
    .INIT ( 64'h9600000000009600 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<1>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [35]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [54]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [5]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [7]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [6]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/expected_data[63]_inv_8_OUT<0> ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<1> )

  );
  LUT6 #(
    .INIT ( 64'h9600000000009600 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<2>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [31]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [50]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [9]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [10]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [8]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/expected_data[63]_inv_8_OUT<0> ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<2> )

  );
  LUT5 #(
    .INIT ( 32'h96000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<3>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [29]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [11]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [48]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [12]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [13]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<3> )

  );
  LUT5 #(
    .INIT ( 32'h96000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<4>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [26]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [14]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [45]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [15]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [16]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<4> )

  );
  LUT5 #(
    .INIT ( 32'h96000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<5>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [23]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [42]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [17]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [18]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [19]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<5> )

  );
  LUT5 #(
    .INIT ( 32'h96000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<6>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [20]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [20]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [39]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [21]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [22]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<6> )

  );
  LUT5 #(
    .INIT ( 32'h96000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<7>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [17]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [23]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [36]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [24]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [25]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<7> )

  );
  LUT5 #(
    .INIT ( 32'h00960000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_GND_30_o_equal_75_o<6>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [20]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [39]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [40]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [38]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_GND_30_o_equal_75_o<6>1 )
  );
  LUT5 #(
    .INIT ( 32'h00960000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_PWR_32_o_equal_77_o<6>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [40]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [19]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [41]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [44]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_PWR_32_o_equal_77_o<6>1 )
  );
  LUT6 #(
    .INIT ( 64'h9600000000009600 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<8>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [13]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [32]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [27]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [28]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [26]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/expected_data[63]_inv_8_OUT<0> ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<8> )

  );
  LUT5 #(
    .INIT ( 32'h96000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<9>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [11]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [30]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [29]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [30]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [31]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<9> )

  );
  LUT6 #(
    .INIT ( 64'h0001000100011000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [4]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/q_542 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/q_541 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<0> )

  );
  LUT5 #(
    .INIT ( 32'h96000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<10>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [27]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [32]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [8]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [33]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [34]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<10> )

  );
  LUT6 #(
    .INIT ( 64'h0001000100011000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<1>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [7]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [9]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [6]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [8]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[2].synch_inst/q_542 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[1].synch_inst/q_541 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<1> )

  );
  LUT5 #(
    .INIT ( 32'h96000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<11>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [24]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [35]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [5]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [36]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [37]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<11> )

  );
  LUT5 #(
    .INIT ( 32'h96000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<12>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [21]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [38]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [39]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [40]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<12> )

  );
  LUT5 #(
    .INIT ( 32'hFFFFFFFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control<1>_SW1_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_PWR_32_o_equal_46_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_PWR_32_o_equal_47_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_PWR_32_o_equal_48_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_PWR_32_o_equal_49_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_GND_30_o_equal_43_o ),
    .O(N516)
  );
  LUT6 #(
    .INIT ( 64'h0240024002400040 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o3  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [4]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [6]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [3]),
    .I4(N282),
    .I5(N516),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o3_5647 )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFFF69FF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_valid_control[3]_AND_122_o1_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [52]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [33]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [7]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [5]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [8]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [6]),
    .O(N518)
  );
  LUT6 #(
    .INIT ( 64'h4000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_valid_control[3]_AND_122_o1  (
    .I0(N518),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_o4[3]_AND_120_o2_4709 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_valid_control[3]_AND_122_o )
  );
  LUT5 #(
    .INIT ( 32'hFFFF96FF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_valid_control[7]_AND_124_o_SW1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [53]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [6]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [34]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [8]),
    .I4(N308),
    .O(N520)
  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_valid_control[7]_AND_124_o  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/o0[3]_o0[3]_OR_331_o ),
    .I1(N520),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [5]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [7]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [6]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [4]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_valid_control[7]_AND_124_o_4803 )
  );
  LUT6 #(
    .INIT ( 64'h777F77FFFFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o12_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [9]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [8]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o11_5655 ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o10_5654 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o21 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_GND_30_o_mux_178_OUT31 ),
    .O(N522)
  );
  LUT6 #(
    .INIT ( 64'h0406040404060606 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_r_type_next_reg[2]_GND_30_o_mux_182_OUT11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I3(N523),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o5_5649 )
,
    .I5(N522),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next_reg[2]_GND_30_o_mux_182_OUT<0> )
  );
  LUT6 #(
    .INIT ( 64'hFF7FFF7FFF7FAA2A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/ignore_next_mismatch_rstpot  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/ignore_next_mismatch_4671 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/rx_66_enc[65]_expected_data[63]_not_equal_9_o ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/rx_66_enc[65]_expected_data[63]_not_equal_7_o ),
    .I3(N525),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/_n0062_inv_4665 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_3_4226 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/ignore_next_mismatch_rstpot_5795 )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFFFEAAA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_r_type_next_reg[2]_GND_30_o_mux_182_OUT2_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_o4[3]_AND_120_o ),
    .I1(N527),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o31 ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_118_o1_4700 )
,
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_valid_control[3]_AND_122_o ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_valid_control[7]_AND_124_o_4803 ),
    .O(N388)
  );
  LUT6 #(
    .INIT ( 64'h5555551D5547550F ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_r_type_next_reg[2]_GND_30_o_mux_182_OUT3  (
    .I0(N382),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o5_5649 )
,
    .I2(N381),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_118_o ),
    .I4(N530),
    .I5(N529),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next_reg[2]_GND_30_o_mux_182_OUT<2> )
  );
  LUT6 #(
    .INIT ( 64'hFAFAFAFAEAEEEAAA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_r_type_next_reg[2]_GND_30_o_mux_182_OUT2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [9]),
    .I2(N533),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o5_5649 )
,
    .I4(N532),
    .I5(N388),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next_reg[2]_GND_30_o_mux_182_OUT<1> )
  );
  LUT5 #(
    .INIT ( 32'hFF69FFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_118_o11_SW0_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [51]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [32]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [8]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [7]),
    .O(N535)
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFA2FFAA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_118_o11_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [4]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [6]),
    .I3(N535),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/o0[3]_o0[3]_OR_331_o ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_GND_30_o_mux_178_OUT312_5644 ),
    .O(N500)
  );
  LUT6 #(
    .INIT ( 64'h96FFFF96FF9696FF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_PWR_32_o_equal_78_o<6>1_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [38]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [21]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [40]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [19]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [0]),
    .O(N537)
  );
  LUT6 #(
    .INIT ( 64'h0000000000000800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_PWR_32_o_equal_78_o<6>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [43]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [39]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [41]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [44]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [42]),
    .I5(N537),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_PWR_32_o_equal_78_o )
  );
  LUT6 #(
    .INIT ( 64'h69FFFF69FF6969FF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_PWR_32_o_equal_77_o<6>2_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [17]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [42]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [40]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [19]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [0]),
    .O(N539)
  );
  LUT6 #(
    .INIT ( 64'h0000000000000400 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_PWR_32_o_equal_77_o<6>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [39]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [38]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [43]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [44]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [41]),
    .I5(N539),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_PWR_32_o_equal_77_o )
  );
  LUT4 #(
    .INIT ( 16'h7DD7 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o12_SW4_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [51]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [32]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [8]),
    .O(N541)
  );
  LUT6 #(
    .INIT ( 64'h1110110000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o12_SW4  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [1]),
    .I1(N541),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o11_5655 ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o10_5654 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o21 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_GND_30_o_mux_178_OUT31 ),
    .O(N532)
  );
  LUT6 #(
    .INIT ( 64'h8228411441148228 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o12_SW2_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [32]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [31]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [50]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [9]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [51]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [8]),
    .O(N543)
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFFFA8A0 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o12_SW2  (
    .I0(N543),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o11_5655 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o10_5654 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o21 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_valid_control[3]_AND_122_o ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_valid_control[7]_AND_124_o_4803 ),
    .O(N529)
  );
  LUT5 #(
    .INIT ( 32'hFFFFFF96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o12_SW3  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [50]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [31]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [9]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_valid_control[3]_AND_122_o ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_valid_control[7]_AND_124_o_4803 ),
    .O(N530)
  );
  LUT6 #(
    .INIT ( 64'h9600000000000069 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/o0[3]_o0[3]_OR_331_o1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [35]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [24]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [36]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [37]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [34]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/o0[3]_o0[3]_OR_331_o )
  );
  LUT4 #(
    .INIT ( 16'hFFFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control<4>_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_GND_30_o_equal_72_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_GND_30_o_equal_74_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_PWR_32_o_equal_78_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_PWR_32_o_equal_77_o ),
    .O(N545)
  );
  LUT6 #(
    .INIT ( 64'h3300320000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_118_o3_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c4[6]_PWR_32_o_equal_79_o ),
    .I1(N384),
    .I2(N408),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_118_o2_5664 )
,
    .I4(N545),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_118_o3_5665 )
,
    .O(N527)
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFD75FDFD ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_all_valid_control_no_Es_AND_118_o11_SW1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [7]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [4]),
    .I2(N547),
    .I3(N548),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/o0[3]_o0[3]_OR_331_o ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_GND_30_o_mux_178_OUT312_5644 ),
    .O(N501)
  );
  LUT3 #(
    .INIT ( 8'hDF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_GND_30_o_mux_178_OUT314_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [1]),
    .I2(N500),
    .O(N550)
  );
  LUT3 #(
    .INIT ( 8'hDF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_GND_30_o_mux_178_OUT314_SW1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [1]),
    .I2(N501),
    .O(N551)
  );
  LUT6 #(
    .INIT ( 64'h00007FFF8000FFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o12_SW5  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [2]),
    .I4(N550),
    .I5(N551),
    .O(N533)
  );
  LUT4 #(
    .INIT ( 16'h9600 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_GND_30_o_mux_178_OUT314_SW2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [50]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [31]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [9]),
    .I3(N500),
    .O(N553)
  );
  LUT4 #(
    .INIT ( 16'h9600 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_GND_30_o_mux_178_OUT314_SW3  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [50]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [31]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [9]),
    .I3(N501),
    .O(N554)
  );
  LUT6 #(
    .INIT ( 64'h00007FFF8000FFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o12_SW1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control [2]),
    .I4(N553),
    .I5(N554),
    .O(N523)
  );
  LUT6 #(
    .INIT ( 64'h010103030105030F ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT72_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_7_4954 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [17]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_303_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_314_o ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<48>2 ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<56>3 ),
    .O(N556)
  );
  LUT6 #(
    .INIT ( 64'h0C0A0C000C0F0C0F ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT72  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [25]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [17]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<48>1 ),
    .I5(N556),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<15> )
  );
  LUT6 #(
    .INIT ( 64'h010103030105030F ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT632_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_0_4948 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [10]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_303_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_314_o ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<48>2 ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<56>3 ),
    .O(N558)
  );
  LUT6 #(
    .INIT ( 64'h0C0A0C000C0F0C0F ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT632  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [18]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [10]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<48>1 ),
    .I5(N558),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<8> )
  );
  LUT6 #(
    .INIT ( 64'h010103030105030F ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT65_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_6_4953 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [16]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_303_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_314_o ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<48>2 ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<56>3 ),
    .O(N560)
  );
  LUT6 #(
    .INIT ( 64'h0C0A0C000C0F0C0F ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT65  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [24]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [16]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<48>1 ),
    .I5(N560),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<14> )
  );
  LUT6 #(
    .INIT ( 64'h010103030105030F ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT53_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_5_4952 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [15]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_303_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_314_o ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<48>2 ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<56>3 ),
    .O(N562)
  );
  LUT6 #(
    .INIT ( 64'h0C0A0C000C0F0C0F ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT53  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [23]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [15]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<48>1 ),
    .I5(N562),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<13> )
  );
  LUT6 #(
    .INIT ( 64'h010103030105030F ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT42_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_4_4951 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [14]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_303_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_314_o ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<48>2 ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<56>3 ),
    .O(N564)
  );
  LUT6 #(
    .INIT ( 64'h0C0A0C000C0F0C0F ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT42  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [22]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [14]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<48>1 ),
    .I5(N564),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<12> )
  );
  LUT6 #(
    .INIT ( 64'h010103030105030F ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT33_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_3_4950 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [13]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_303_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_314_o ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<48>2 ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<56>3 ),
    .O(N566)
  );
  LUT6 #(
    .INIT ( 64'h0C0A0C000C0F0C0F ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT33  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [21]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [13]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<48>1 ),
    .I5(N566),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<11> )
  );
  LUT6 #(
    .INIT ( 64'h0001010155555555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT2_SW1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_303_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_305_o ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<39>2 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_315_o<7>1 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_304_o<7>1 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [20]),
    .O(N568)
  );
  LUT6 #(
    .INIT ( 64'h5555101110111011 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<48>2 ),
    .I3(N568),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [12]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT111_4674 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<10> )
  );
  LUT6 #(
    .INIT ( 64'h0001010100555555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT10_SW1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_303_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_305_o ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<39>2 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_304_o<7>1 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_315_o<7>1 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [28]),
    .O(N570)
  );
  LUT6 #(
    .INIT ( 64'h5555101110111011 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT10  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<48>2 ),
    .I3(N570),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [20]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT111_4674 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<18> )
  );
  LUT5 #(
    .INIT ( 32'h1133153F ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT642_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c1_1_4949 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [11]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_314_o ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<48>2 ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<56>3 ),
    .O(N572)
  );
  LUT6 #(
    .INIT ( 64'h0C0A0C000C0F0C0F ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT642  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [19]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [11]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<48>1 ),
    .I5(N572),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<9> )
  );
  LUT6 #(
    .INIT ( 64'h010105050103050F ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT251_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [33]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [41]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_305_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_314_o ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<39>2 ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<56>3 ),
    .O(N574)
  );
  LUT6 #(
    .INIT ( 64'h0C0A0C000C0F0C0F ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT252  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_7_4968 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [33]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<39>3 ),
    .I5(N574),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<31> )
  );
  LUT6 #(
    .INIT ( 64'h010105050103050F ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT241_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [32]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [40]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_305_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_314_o ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<39>2 ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<56>3 ),
    .O(N576)
  );
  LUT6 #(
    .INIT ( 64'h0C0A0C000C0F0C0F ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT242  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_6_4967 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [32]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<39>3 ),
    .I5(N576),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<30> )
  );
  LUT6 #(
    .INIT ( 64'h010105050103050F ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT221_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [31]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [39]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_305_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_314_o ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<39>2 ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<56>3 ),
    .O(N578)
  );
  LUT6 #(
    .INIT ( 64'h0C0A0C000C0F0C0F ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT222  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_5_4966 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [31]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<39>3 ),
    .I5(N578),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<29> )
  );
  LUT6 #(
    .INIT ( 64'h010105050103050F ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT211_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [30]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [38]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_305_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_314_o ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<39>2 ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<56>3 ),
    .O(N580)
  );
  LUT6 #(
    .INIT ( 64'h0C0A0C000C0F0C0F ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT212  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_4_4965 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [30]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<39>3 ),
    .I5(N580),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<28> )
  );
  LUT6 #(
    .INIT ( 64'h010105050103050F ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT201_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [29]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [37]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_305_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_314_o ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<39>2 ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<56>3 ),
    .O(N582)
  );
  LUT6 #(
    .INIT ( 64'h0C0A0C000C0F0C0F ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT202  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c3_3_4964 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [29]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<39>3 ),
    .I5(N582),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<27> )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFA8FFA8FFA8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT34_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [13]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<29>2 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<39>2 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_314_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_3_4943 ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<56>2 ),
    .O(N312)
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFA8FFA8FFA8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT45_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [14]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<29>2 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<39>2 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_314_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_4_4944 ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<56>2 ),
    .O(N314)
  );
  LUT5 #(
    .INIT ( 32'hFFA8A8A8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT613  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [16]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<29>2 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<39>2 ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<56>2 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_6_4946 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT612_5631 )
  );
  LUT5 #(
    .INIT ( 32'hFFA8A8A8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT623  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [17]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<29>2 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<39>2 ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<56>2 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_7_4947 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT622_5634 )
  );
  LUT5 #(
    .INIT ( 32'hFFA8A8A8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT56_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [15]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<29>2 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<39>2 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_5_4945 ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<56>2 ),
    .O(N338)
  );
  LUT5 #(
    .INIT ( 32'h01110FFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT12_SW0  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<29>2 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<39>2 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<56>2 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_1_4942 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [11]),
    .O(N340)
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFFFFFA8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT23_SW0_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [12]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<39>2 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<29>2 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_312_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_315_o ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_313_o ),
    .O(N404)
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFAAAAAAA8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT3311_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_4_4972 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_302_o ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<29>2 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_315_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_301_o ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<24>3 ),
    .O(N488)
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFAAAAAAA8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT3311_SW1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_3_4971 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_302_o ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<29>2 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_315_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_301_o ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<24>3 ),
    .O(N490)
  );
  LUT5 #(
    .INIT ( 32'h10080000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<16>2_SW1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [8]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [7]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [9]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_315_o<7>1 ),
    .O(N586)
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFFFFFFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<16>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_306_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_305_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_303_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_302_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_301_o ),
    .I5(N586),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<16>2_4714 )

  );
  LUT6 #(
    .INIT ( 64'h8241800102400000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<39>21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [5]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [6]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [4]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_306_o<7>1 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_308_o<7>1 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<39>2 )
  );
  LUT6 #(
    .INIT ( 64'h4545454544444440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT82  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [18]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<56>3 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_314_o ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT8 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<16> )
  );
  LUT6 #(
    .INIT ( 64'h4545454544444440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT162  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [25]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<56>3 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_314_o ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT16 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<23> )
  );
  LUT6 #(
    .INIT ( 64'h4545454544444440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT152  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [24]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<56>3 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_314_o ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT15 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<22> )
  );
  LUT6 #(
    .INIT ( 64'h4545454544444440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT142  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [23]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<56>3 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_314_o ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT14 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<21> )
  );
  LUT6 #(
    .INIT ( 64'h4545454544444440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT132  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [22]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<56>3 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_314_o ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT13 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<20> )
  );
  LUT6 #(
    .INIT ( 64'h4545454544444440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT112  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [21]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<56>3 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_314_o ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT11 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<19> )
  );
  LUT6 #(
    .INIT ( 64'h00EF00CF00AA0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT422  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [49]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4675 )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT42_5575 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<47> )
  );
  LUT6 #(
    .INIT ( 64'h00EF00CF00AA0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT412  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [48]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4675 )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT41 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<46> )
  );
  LUT6 #(
    .INIT ( 64'h00EF00CF00AA0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT402  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [47]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4675 )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT40 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<45> )
  );
  LUT6 #(
    .INIT ( 64'h00EF00CF00AA0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT392  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [46]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4675 )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT39 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<44> )
  );
  LUT6 #(
    .INIT ( 64'h00EF00CF00AA0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT382  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [45]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4675 )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT38 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<43> )
  );
  LUT6 #(
    .INIT ( 64'h00EF00CF00AA0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT352  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [42]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4675 )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT35 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<40> )
  );
  LUT6 #(
    .INIT ( 64'h5555551045454500 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT614  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [1]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT612_5631 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT611 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [8]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<6> )
  );
  LUT6 #(
    .INIT ( 64'h00FD00FD002000FD ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT12  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I4(N340),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT5611 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<1> )
  );
  LUT6 #(
    .INIT ( 64'h5555555544444440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT92  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [19]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[1]_PWR_32_o_equal_300_o ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<56>3 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_314_o ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT9 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<17> )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFF00010000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<7>21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [4]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [5]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [6]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_308_o<7>1 ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<10>1 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<7>2 )
  );
  LUT6 #(
    .INIT ( 64'hBBBBB000B000B000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT91  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c2_1_4956 ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<40>2 ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<40>1 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [27]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT9 )
  );
  LUT6 #(
    .INIT ( 64'hEE0EAA0ACC0C0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT441  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c6_1_4984 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [59]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_309_o ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<10>1 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT44 )
  );
  LUT5 #(
    .INIT ( 32'h96FFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]_o4[3]_AND_120_o2_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [31]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [50]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [9]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [4]),
    .O(N320)
  );
  LUT5 #(
    .INIT ( 32'h969669FF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_GND_30_o_mux_178_OUT311_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [38]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [57]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [8]),
    .O(N547)
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFF96FFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_GND_30_o_mux_178_OUT311_SW1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [38]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [57]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [8]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [3]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [6]),
    .O(N548)
  );
  LUT5 #(
    .INIT ( 32'h96000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<13>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [18]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [41]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [42]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [43]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<13> )

  );
  LUT5 #(
    .INIT ( 32'h96000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<14>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [15]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [44]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [5]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [45]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [46]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<14> )

  );
  LUT5 #(
    .INIT ( 32'h96000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<15>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [12]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [47]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [8]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [48]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [49]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<15> )

  );
  LUT5 #(
    .INIT ( 32'h96000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<16>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [9]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [50]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [11]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [51]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [52]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<16> )

  );
  LUT5 #(
    .INIT ( 32'h96000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<17>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [6]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [53]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [14]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [54]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [55]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<17> )

  );
  LUT6 #(
    .INIT ( 64'h9600000000009600 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<18>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [56]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [17]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [57]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [58]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/expected_data[63]_inv_8_OUT<0> ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<18> )

  );
  LUT5 #(
    .INIT ( 32'h96000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<19>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [20]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [59]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [60]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [61]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<19> )

  );
  LUT5 #(
    .INIT ( 32'h96000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<20>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [23]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [62]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [4]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [63]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [64]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_9_o_lut<20> )

  );
  LUT5 #(
    .INIT ( 32'hFFFFFFFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<40>21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_311_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_302_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_301_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_310_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_303_o ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<40>2 )
  );
  MUXF7 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11116_SW0  (
    .I0(N588),
    .I1(N589),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT522 ),
    .O(N506)
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFF55545555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11116_SW0_F  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11111_5335 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[3]_AND_61_o )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[2]_AND_57_o )
,
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[1]_AND_52_o )
,
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT111112 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out232 ),
    .O(N588)
  );
  MUXF7 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11114_SW0  (
    .I0(N590),
    .I1(N0),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[5]_AND_66_o )
,
    .O(N513)
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFF57FF54FC ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11114_SW0_F  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11112_5336 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [6]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11411 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1141 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[63]_PWR_23_o_equal_148_o ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[4]_AND_64_o )
,
    .O(N590)
  );
  MUXF7 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11114_SW1  (
    .I0(N592),
    .I1(N0),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[5]_AND_66_o )
,
    .O(N514)
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFF444F4440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11114_SW1_F  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11112_5336 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1141 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11411 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [6]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[63]_PWR_23_o_equal_148_o ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[4]_AND_64_o )
,
    .O(N592)
  );
  LUT5 #(
    .INIT ( 32'h2E2EAAA2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/hiber_rstpot  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4510 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/hiber_rstpot_5771 )
  );
  LUT3 #(
    .INIT ( 8'h9A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/newedge_rstpot  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/newedge_3380 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/d1_3379 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_1_3392 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/newedge_rstpot_5780 )
  );
  LUT3 #(
    .INIT ( 8'h9A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/newedge_rstpot  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/newedge_3384 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/d1_3383 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_2_3394 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/newedge_rstpot_5781 )
  );
  LUT3 #(
    .INIT ( 8'h9A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/newedge_rstpot  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/newedge_3388 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/d1_3387 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_3_3393 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/newedge_rstpot_5782 )
  );
  LUT3 #(
    .INIT ( 8'h9A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/newedge_rstpot  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/newedge_3400 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/d1_3399 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_1_3412 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/newedge_rstpot_5783 )
  );
  LUT3 #(
    .INIT ( 8'h9A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/newedge_rstpot  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/newedge_3404 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/d1_3403 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_2_3414 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/newedge_rstpot_5784 )
  );
  LUT3 #(
    .INIT ( 8'h9A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/newedge_rstpot  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/newedge_3408 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/d1_3407 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_3_3413 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/newedge_rstpot_5785 )
  );
  LUT3 #(
    .INIT ( 8'h9A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/newedge_rstpot  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/newedge_3420 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/d1_3419 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_1_3432 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/newedge_rstpot_5786 )
  );
  LUT3 #(
    .INIT ( 8'h9A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/newedge_rstpot  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/newedge_3424 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/d1_3423 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_2_3434 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/newedge_rstpot_5787 )
  );
  LUT3 #(
    .INIT ( 8'h9A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/newedge_rstpot  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/newedge_3428 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/d1_3427 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_3_3433 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/newedge_rstpot_5788 )
  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_slip_rstpot  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_slip_reg_502 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_slip_int_reg_499 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/gt_slip_rstpot_5772 )
  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_rx_link_up_core_reg_rstpot  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[1].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_806_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_rx_link_up_core_reg_rstpot_5773 )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFF808080D5 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT145_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_GND_22_o_equal_165_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_166_o ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[7]_tx_xgmii_data_reg1[7]_OR_155_o_3589 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_GND_22_o_equal_181_o ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_PWR_23_o_equal_185_o_mmx_out1 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1141 ),
    .O(N594)
  );
  LUT6 #(
    .INIT ( 64'h5555545555551011 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT145  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[3]_AND_61_o )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[5]_AND_66_o )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT142_5332 ),
    .I3(N594),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[4]_AND_64_o )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[55]_PWR_23_o_equal_142_o_mmx_out_3506 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT145_5333 )
  );
  LUT2 #(
    .INIT ( 4'hD ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd2_rstpot_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/can_insert_rd ),
    .I1(reset),
    .O(N598)
  );
  LUT6 #(
    .INIT ( 64'h1000100400000004 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd2_rstpot  (
    .I0(N598),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd3_3332 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd1_3334 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd2_3333 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd2_rstpot_5778 )
  );
  LUT2 #(
    .INIT ( 4'hD ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd1_rstpot_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd3_3332 ),
    .I1(reset),
    .O(N600)
  );
  LUT6 #(
    .INIT ( 64'h5555515555555555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd1_rstpot  (
    .I0(N600),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/can_insert_rd ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd2_3333 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_is_idle_or_seq [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd1_3334 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/state_FSM_FFd1_rstpot_5779 )
  );
  LUT6 #(
    .INIT ( 64'hFFFFAA08AA08AA08 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT463_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d5 [0]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [5]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>1 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d6 [0]),
    .O(N602)
  );
  LUT5 #(
    .INIT ( 32'h55554440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT463  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c5 [5]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_448_o ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<28>1 ),
    .I4(N602),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<50> )
  );
  LUT6 #(
    .INIT ( 64'hFFFFAA08AA08AA08 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT473_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d5 [1]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [5]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>1 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d6 [1]),
    .O(N604)
  );
  LUT5 #(
    .INIT ( 32'h55554440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT473  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c5 [6]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_448_o ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<28>1 ),
    .I4(N604),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<51> )
  );
  LUT4 #(
    .INIT ( 16'hDDFD ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int_0_glue_set  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [0]),
    .I1(txreset322),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/_n00791_2243 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/read_enable_2252 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int_0_glue_set_5675 )
  );
  LUT4 #(
    .INIT ( 16'h0008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/indirect_read_rstpot  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]),
    .I3(reset),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/indirect_read_rstpot_5776 )
  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/read_enable_rstpot_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [6]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [5]),
    .O(N606)
  );
  LUT6 #(
    .INIT ( 64'h0111111111111111 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/read_enable_rstpot  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/read_enable_2252 ),
    .I1(txreset322),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [2]),
    .I4(N52),
    .I5(N606),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/read_enable_rstpot_5777 )
  );
  LUT6 #(
    .INIT ( 64'h1505140411011000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT92  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_all/q [2]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT91 )

  );
  LUT6 #(
    .INIT ( 64'h5450141044400400 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT112  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [4]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [4]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [4]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT111 )

  );
  LUT6 #(
    .INIT ( 64'h5450141044400400 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT107  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT106 )

  );
  LUT4 #(
    .INIT ( 16'hFF7F ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/_n0050_SW1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[3].synch_inst/q_543 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_806_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_3_4226 ),
    .O(N525)
  );
  LUT3 #(
    .INIT ( 8'hA8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_rstpot  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/emptyg ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_en ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_rstpot_5768 )
  );
  LUT4 #(
    .INIT ( 16'hFA8A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/b_lock_rstpot  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_806_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3_4394 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1_4422 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/b_lock_rstpot_5770 )
  );
  LUT4 #(
    .INIT ( 16'hFF8A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_14/q_0_rstpot  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_14/q_0_1952 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_15/re_prev_1998 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_re ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_32_1/q_0_1955 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_14/q_0_rstpot_5762 )
  );
  LUT4 #(
    .INIT ( 16'hAA08 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_15/q_0_rstpot  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_32_0/q_0_1954 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_re ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_15/re_prev_1998 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_15/q_0_1953 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_15/q_0_rstpot_5763 )
  );
  LUT3 #(
    .INIT ( 8'h10 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_we_rising_rstpot  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_we_reg_1340 ),
    .I1(reset),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/we_1362 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_we_rising_rstpot_5774 )
  );
  LUT3 #(
    .INIT ( 8'h10 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_rstpot  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_reg3_1342 ),
    .I1(reset),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_reg2_1344 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_rstpot_5775 )
  );
  LUT5 #(
    .INIT ( 32'hFFFF8880 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT176_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[3]_reduce_and_158_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1141 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_166_o ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_tx_xgmii_data_reg1[39]_OR_153_o_3588 )
,
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT173 ),
    .O(N612)
  );
  LUT6 #(
    .INIT ( 64'h20202000A8A8A888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT176  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT171_5327 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[5]_AND_66_o )
,
    .I2(N612),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [6]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11411 ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[55]_PWR_23_o_equal_142_o_mmx_out_3506 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT175 )
  );
  LUT6 #(
    .INIT ( 64'h0001010100555555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT1_SW1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_302_o ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<39>2 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<29>2 ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<56>2 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c0_0_4941 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [10]),
    .O(N614)
  );
  LUT6 #(
    .INIT ( 64'h5510555545004545 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_314_o ),
    .I4(N614),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<0> )
  );
  LUT6 #(
    .INIT ( 64'h8000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o7_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [58]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [59]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [60]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [61]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [62]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [63]),
    .O(N616)
  );
  LUT6 #(
    .INIT ( 64'h8000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o12_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [34]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [35]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [36]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [37]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [38]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [39]),
    .O(N618)
  );
  LUT6 #(
    .INIT ( 64'h8000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o17_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [18]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [19]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [20]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [21]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [22]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [23]),
    .O(N620)
  );
  LUT3 #(
    .INIT ( 8'hA8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/empty_int_rstpot  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/emptyg ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/read_enable_2252 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/empty_int_2366 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/empty_int_rstpot_5767 )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFF20002202 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_6_glue_set  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1162 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[2]_AND_57_o )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[3]_AND_61_o )
,
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_126_o_mmx_out1 )
,
    .I4(N622),
    .I5(N392),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_6_glue_set_5687 )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFFF1011 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_2_glue_set  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out232 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[1]_AND_52_o )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT81_5323 ),
    .I3(N624),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n0915 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT8 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_2_glue_set_5691 )
  );
  LUT5 #(
    .INIT ( 32'hAA80AAAA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0262_inv1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1341 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3_1497 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2_1496 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count_load_value [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/n0027 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0262_inv )
  );
  LUT4 #(
    .INIT ( 16'hEA2A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_shift_reg[14]_data_captured[15]_mux_73_OUT17  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/mdio_in_reg_1632 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_351_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [0]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<0> )

  );
  LUT4 #(
    .INIT ( 16'hEA2A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_shift_reg[14]_data_captured[15]_mux_73_OUT21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [9]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_351_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [10]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<10> )

  );
  LUT4 #(
    .INIT ( 16'hEA2A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_shift_reg[14]_data_captured[15]_mux_73_OUT31  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [10]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_351_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [11]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<11> )

  );
  LUT4 #(
    .INIT ( 16'hEA2A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_shift_reg[14]_data_captured[15]_mux_73_OUT41  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [11]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_351_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [12]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<12> )

  );
  LUT4 #(
    .INIT ( 16'hEA2A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_shift_reg[14]_data_captured[15]_mux_73_OUT51  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [12]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_351_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [13]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<13> )

  );
  LUT4 #(
    .INIT ( 16'hEA2A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_shift_reg[14]_data_captured[15]_mux_73_OUT61  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [13]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_351_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [14]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<14> )

  );
  LUT4 #(
    .INIT ( 16'hEA2A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_shift_reg[14]_data_captured[15]_mux_73_OUT71  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [14]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_351_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [15]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<15> )

  );
  LUT4 #(
    .INIT ( 16'hEA2A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_shift_reg[14]_data_captured[15]_mux_73_OUT81  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [0]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_351_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<1> )

  );
  LUT4 #(
    .INIT ( 16'hEA2A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_shift_reg[14]_data_captured[15]_mux_73_OUT91  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [1]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_351_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<2> )

  );
  LUT4 #(
    .INIT ( 16'hEA2A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_shift_reg[14]_data_captured[15]_mux_73_OUT101  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [2]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_351_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<3> )

  );
  LUT4 #(
    .INIT ( 16'hEA2A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_shift_reg[14]_data_captured[15]_mux_73_OUT111  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [3]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_351_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [4]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<4> )

  );
  LUT4 #(
    .INIT ( 16'hEA2A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_shift_reg[14]_data_captured[15]_mux_73_OUT121  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [4]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_351_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [5]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<5> )

  );
  LUT4 #(
    .INIT ( 16'hEA2A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_shift_reg[14]_data_captured[15]_mux_73_OUT131  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [5]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_351_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [6]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<6> )

  );
  LUT4 #(
    .INIT ( 16'hEA2A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_shift_reg[14]_data_captured[15]_mux_73_OUT141  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [6]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_351_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [7]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<7> )

  );
  LUT4 #(
    .INIT ( 16'hEA2A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_shift_reg[14]_data_captured[15]_mux_73_OUT151  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [7]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_351_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [8]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<8> )

  );
  LUT4 #(
    .INIT ( 16'hEA2A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mmux_shift_reg[14]_data_captured[15]_mux_73_OUT161  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [8]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_351_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/data_captured [9]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg[14]_data_captured[15]_mux_73_OUT<9> )

  );
  LUT6 #(
    .INIT ( 64'h9696966996699696 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT91  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [11]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [50]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [31]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [9]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [48]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT9 )

  );
  LUT6 #(
    .INIT ( 64'h9696966996699696 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT81  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [10]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [49]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [30]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [10]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [49]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT8 )

  );
  LUT6 #(
    .INIT ( 64'h9696966996699696 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT71  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [9]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [48]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [29]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [11]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [50]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT7 )

  );
  LUT6 #(
    .INIT ( 64'h9696966996699696 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT61  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [8]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [47]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [28]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [12]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [51]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT6 )

  );
  LUT6 #(
    .INIT ( 64'h9696966996699696 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT51  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [7]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [46]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [27]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [13]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [52]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT5 )

  );
  LUT6 #(
    .INIT ( 64'h9696966996699696 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT581  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [42]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [23]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [17]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [56]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT58 )

  );
  LUT6 #(
    .INIT ( 64'h9696966996699696 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT571  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [41]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [22]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [18]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [57]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT57 )

  );
  LUT5 #(
    .INIT ( 32'hFFA8A8A8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT28_SW1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d3 [0]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>31 )
,
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<31>2 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d4 [0]),
    .O(N626)
  );
  LUT6 #(
    .INIT ( 64'h5555555555555540 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT28  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c3 [3]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<31>1 ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT2811 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>2 ),
    .I5(N626),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<34> )
  );
  LUT5 #(
    .INIT ( 32'hFFA8A8A8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT29_SW1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d3 [1]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>31 )
,
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<31>2 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d4 [1]),
    .O(N628)
  );
  LUT6 #(
    .INIT ( 64'h5555555555555540 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT29  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c3 [4]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<31>1 ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT2811 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>2 ),
    .I5(N628),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<35> )
  );
  LUT5 #(
    .INIT ( 32'hFF808080 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT15_SW0  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1726 )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[20]_GND_44_o_equal_101_o<20>1 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q [0]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_PWR_46_o_equal_60_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [0]),
    .O(N630)
  );
  LUT6 #(
    .INIT ( 64'hEAEAEAEAFFEAEAEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT15  (
    .I0(N630),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [0]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_46_o ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_35_o<15>1_1724 )
,
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT110_5287 )

  );
  LUT6 #(
    .INIT ( 64'h22A800A822200020 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT110  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_48_o<15>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q [0]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT128_5292 )

  );
  LUT6 #(
    .INIT ( 64'h22A800A822200020 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT88  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_48_o<15>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT87_5300 )

  );
  LUT6 #(
    .INIT ( 64'hAAA22022FFFBBABB ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Msub_wr_addr_pipe[3]_ra_writesync[3]_sub_81_OUT_cy<2>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ra_writesync [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ra_writesync [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Msub_wr_addr_pipe[3]_ra_writesync[3]_sub_81_OUT_cy<2> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFEFFFEFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT1111  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_315_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_312_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_314_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_313_o ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT111_4674 )
  );
  LUT4 #(
    .INIT ( 16'hFFFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT612_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [34]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [35]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [36]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [37]),
    .O(N632)
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFFFAAA8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT612  (
    .I0(N632),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_312_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_313_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_315_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_302_o ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_314_o ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT611 )
  );
  LUT4 #(
    .INIT ( 16'h7FFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT622_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [34]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [35]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [36]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [37]),
    .O(N634)
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFFFAAA8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT622  (
    .I0(N634),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_312_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_313_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_315_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_302_o ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_314_o ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT621 )
  );
  LUT6 #(
    .INIT ( 64'h23DCDC232AD5D52A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Msub_wr_addr_pipe[3]_ra_writesync[3]_sub_81_OUT_xor<2>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ra_writesync [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ra_writesync [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe [2]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync [0]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr_pipe[3]_ra_writesync[3]_sub_81_OUT<2> )

  );
  LUT4 #(
    .INIT ( 16'h8000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int_6_glue_set_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [5]),
    .O(N636)
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFF6A6AFF6A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int_6_glue_set  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int [6]),
    .I1(N636),
    .I2(N52),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/_n00791_2243 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/read_enable_2252 ),
    .I5(txreset322),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/txsequence_int_6_glue_set_5676 )
  );
  LUT6 #(
    .INIT ( 64'h2222200020002000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT16  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_PWR_46_o_equal_57_o<15>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q [0]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT117_5288 )

  );
  LUT6 #(
    .INIT ( 64'h2222200020002000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT84  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_PWR_46_o_equal_57_o<15>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT83_5296 )

  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_45_o<15>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_45_o )
  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_46_o<15>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_46_o )
  );
  LUT6 #(
    .INIT ( 64'hFFFFF888F888F888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT123_SW0  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_PWR_46_o_equal_57_o<15>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q [5]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[20]_GND_44_o_equal_101_o<20>1 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q [5]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [5]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .O(N638)
  );
  LUT5 #(
    .INIT ( 32'h40404000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT123  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT12_5228 )
,
    .I4(N638),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT122 )

  );
  LUT6 #(
    .INIT ( 64'h2020200000200000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n02561  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_match_1644 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_351_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_cs ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rdack_1245 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [16]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0256 )
  );
  LUT5 #(
    .INIT ( 32'h88800800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0271_inv1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_351_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_cs ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rdack_1245 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [16]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0271_inv )
  );
  LUT6 #(
    .INIT ( 64'h8000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_PWR_46_o_equal_60_o<15>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode11_5302 ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode12_5303 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_PWR_46_o_equal_60_o )
  );
  LUT6 #(
    .INIT ( 64'h2112844884482112 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [52]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [38]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [7]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [33]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [57]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o1_5645 )
  );
  LUT6 #(
    .INIT ( 64'h1221488448841221 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o7  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [35]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [36]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [54]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [5]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [55]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [4]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o7_5651 )
  );
  LUT6 #(
    .INIT ( 64'h1221488448841221 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [34]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [37]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [53]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [6]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [56]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [3]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o11_5655 )
  );
  LUT5 #(
    .INIT ( 32'h82800200 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT146  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [7]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q [7]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT145_5210 )

  );
  LUT5 #(
    .INIT ( 32'h14100400 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT101  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT10 )

  );
  LUT5 #(
    .INIT ( 32'h14100400 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT124  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q [5]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q [5]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT123_5230 )

  );
  LUT5 #(
    .INIT ( 32'h14100400 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT153  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q [8]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q [8]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT152_5243 )

  );
  LUT5 #(
    .INIT ( 32'h14100400 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT43  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q [12]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q [12]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT42_5250 )

  );
  LUT5 #(
    .INIT ( 32'h14100400 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT163  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q [9]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q [9]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT162_5257 )

  );
  LUT5 #(
    .INIT ( 32'h14100400 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT54  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q [13]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q [13]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT53_5266 )

  );
  LUT5 #(
    .INIT ( 32'h14100400 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT73  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q [15]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q [15]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT72_5272 )

  );
  LUT5 #(
    .INIT ( 32'h14100400 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT23  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q [10]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q [10]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT22_5279 )

  );
  LUT6 #(
    .INIT ( 64'h8684060482800200 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT155  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/q [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q [8]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [8]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT154_5245 )

  );
  LUT6 #(
    .INIT ( 64'h8684060482800200 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT45  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/q [4]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q [12]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [12]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT44_5252 )

  );
  LUT6 #(
    .INIT ( 64'h8684060482800200 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT165  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/q [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q [9]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [9]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT164_5259 )

  );
  LUT6 #(
    .INIT ( 64'h8684060482800200 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT53  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/q [5]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q [13]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [13]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT52_5265 )

  );
  LUT6 #(
    .INIT ( 64'h8684060482800200 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT75  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_15/q_0_1953 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q [15]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [15]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT74_5274 )

  );
  LUT6 #(
    .INIT ( 64'h8684060482800200 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT25  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/q [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q [10]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [10]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT24_5281 )

  );
  LUT5 #(
    .INIT ( 32'h14100400 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT114  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q [4]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q [4]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT113_5216 )

  );
  LUT5 #(
    .INIT ( 32'h82800200 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT105  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT104_5224 )

  );
  LUT5 #(
    .INIT ( 32'h14100400 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT63  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q [14]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q [14]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT62_5237 )

  );
  LUT6 #(
    .INIT ( 64'h8684060482800200 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT65  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_14/q_0_1952 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q [14]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [14]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT64_5239 )

  );
  LUT6 #(
    .INIT ( 64'h0440004004000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/out8_SW1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [6]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [4]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [5]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_310_o<7>1 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_312_o<7>1 ),
    .O(N418)
  );
  LUT5 #(
    .INIT ( 32'hFEFEFEFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c3[6]_mux_228_OUT21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_GND_30_o_equal_63_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_69_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_GND_30_o_equal_62_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_68_o ),
    .I4(N370),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c3[6]_mux_228_OUT<1> )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFEFEFEFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c3[6]_mux_228_OUT71  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_GND_30_o_equal_63_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_69_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_68_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_GND_30_o_equal_62_o ),
    .I4(N370),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_66_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c3[6]_mux_228_OUT<6> )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFEFEFEFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c3[6]_mux_228_OUT81  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_GND_30_o_equal_63_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_69_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_68_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_GND_30_o_equal_62_o ),
    .I4(N370),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_67_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c3[6]_mux_228_OUT<7> )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFFF01FF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c3[6]_mux_228_OUT4  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_GND_30_o_equal_62_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_69_o ),
    .I2(N370),
    .I3(N330),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_PWR_32_o_equal_68_o ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_GND_30_o_equal_63_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c3[6]_mux_228_OUT<3> )
  );
  LUT3 #(
    .INIT ( 8'h96 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Mxor_ra_writesync<1>_xo<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rag_writesync [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/ra_writesync [1])
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFFF111F ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT12311  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2_5068 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5069 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/next_state [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/next_state [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_6_4223 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/next_state [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1231_5064 )
  );
  LUT6 #(
    .INIT ( 64'h000E000E000E0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT11041  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/next_state [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/next_state [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/next_state [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_6_4223 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2_5068 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5069 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1104 )
  );
  LUT6 #(
    .INIT ( 64'h96FFFF96FF9696FF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o211_SW1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [57]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [38]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [35]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [54]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [5]),
    .O(N416)
  );
  LUT5 #(
    .INIT ( 32'hFFFEFEFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT3311_SW2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_306_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_310_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_312_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_314_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [41]),
    .O(N492)
  );
  LUT4 #(
    .INIT ( 16'h0002 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode211  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_35_o<15>1_1724 )

  );
  LUT6 #(
    .INIT ( 64'hDFFFFFFFFFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[31]_PWR_23_o_equal_118_o1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [24]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [25]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [27]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[31]_tx_xgmii_data_reg1[31]_OR_80_o2 )
,
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[4] ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out1411 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[31]_PWR_23_o_equal_118_o_mmx_out )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFF00010000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c6[6]_mux_261_OUT11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [53]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [54]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [55]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [56]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_GND_30_o_equal_92_o<6>1 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c6[6]_PWR_32_o_equal_99_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c6[6]_mux_261_OUT<0> )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFF00010000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c5[6]_mux_250_OUT11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [46]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [47]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [48]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [49]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_GND_30_o_equal_82_o<6>1 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c5[6]_PWR_32_o_equal_89_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c5[6]_mux_250_OUT<0> )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFF00010000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c7[6]_mux_272_OUT11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [60]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [61]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [62]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [63]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_GND_30_o_equal_102_o<6>1 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c7[6]_PWR_32_o_equal_109_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c7[6]_mux_272_OUT<0> )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFF00010000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c2[6]_mux_217_OUT11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [25]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [26]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [27]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [28]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_GND_30_o_equal_52_o<6>1 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c2[6]_PWR_32_o_equal_59_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c2[6]_mux_217_OUT<0> )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFF00010000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c0[6]_mux_195_OUT11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [11]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [12]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [13]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [14]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_GND_30_o_equal_32_o<6>1 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c0[6]_PWR_32_o_equal_39_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c0[6]_mux_195_OUT<0> )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFF00010000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c1[6]_mux_206_OUT11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [18]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [19]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [20]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [21]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_GND_30_o_equal_42_o<6>1 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c1[6]_PWR_32_o_equal_49_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c1[6]_mux_206_OUT<0> )
  );
  LUT6 #(
    .INIT ( 64'h0000000100010000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2-In1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [4]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2-In1_5557 )
  );
  LUT6 #(
    .INIT ( 64'h7FFFFFFFFFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT46_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_308_o<7>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [6]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [4]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [5]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [60]),
    .O(N346)
  );
  LUT5 #(
    .INIT ( 32'h2AAAAAAA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11112  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[1]_AND_52_o )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[3] ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[4] ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out1411 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[23]_PWR_23_o_equal_110_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11111_5335 )
  );
  LUT3 #(
    .INIT ( 8'hF2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/_n0201_inv1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_en ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I2(reset),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/_n0201_inv )
  );
  LUT6 #(
    .INIT ( 64'h0000010001010101 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>21  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_448_o ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_453_o<7>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [2]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_445_o<7>1 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>21_5404 )

  );
  LUT6 #(
    .INIT ( 64'h5555400040004000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT131  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q [6]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q [6]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode1 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT13_5197 )

  );
  LUT6 #(
    .INIT ( 64'h0111051501110111 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT10_SW0  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>22_5405 )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c1 [1]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [2]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [1]),
    .O(N168)
  );
  LUT6 #(
    .INIT ( 64'h0111051501110111 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT11_SW0  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>22_5405 )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c1 [2]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [2]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [1]),
    .O(N170)
  );
  LUT6 #(
    .INIT ( 64'h0111051501110111 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT13_SW0  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>22_5405 )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c1 [3]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [2]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [1]),
    .O(N172)
  );
  LUT6 #(
    .INIT ( 64'h0111051501110111 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT14_SW0  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>22_5405 )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c1 [4]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [2]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [1]),
    .O(N174)
  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_52_o<15>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_52_o )
  );
  LUT5 #(
    .INIT ( 32'h00800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT142111  (
    .I0(pma_pmd_type[2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_35_o<15>1_1724 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I4(pma_pmd_type[1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT14211 )

  );
  LUT6 #(
    .INIT ( 64'h2AAAAAAAAAAAAAAA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT111211  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1141 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_166_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[3] ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[2] ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[1] ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[0] ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11121 )
  );
  LUT5 #(
    .INIT ( 32'h80000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out1421  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[2] ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[3] ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[4] ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out1411 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[1] ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out142 )
  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_445_o<7>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [7]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [6]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [5]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [4]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_445_o<7>1 )
  );
  LUT6 #(
    .INIT ( 64'h8000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1171  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[3] ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[4] ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out1411 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[2] ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[15]_PWR_23_o_equal_102_o ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out232 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT117 )
  );
  LUT6 #(
    .INIT ( 64'h0004040400555555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT26_SW0  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>22_5405 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [2]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<31>1 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c3 [1]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o ),
    .O(N204)
  );
  LUT6 #(
    .INIT ( 64'h0004040400555555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT27_SW0  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>22_5405 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [2]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<31>1 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c3 [2]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o ),
    .O(N206)
  );
  LUT5 #(
    .INIT ( 32'hFFABFFA8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_delay [4]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I3(rxreset322),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe [0]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out[7]_GND_34_o_mux_32_OUT<0> )

  );
  LUT5 #(
    .INIT ( 32'hFFABFFA8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1171  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [56]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I3(rxreset322),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [24]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<24> )

  );
  LUT5 #(
    .INIT ( 32'hFFABFFA8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1231  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [34]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I3(rxreset322),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<2> )

  );
  LUT5 #(
    .INIT ( 32'hFFABFFA8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1281  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [2]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I3(rxreset322),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [34]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<34> )

  );
  LUT5 #(
    .INIT ( 32'hFFABFFA8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1291  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [3]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I3(rxreset322),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [35]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<35> )

  );
  LUT5 #(
    .INIT ( 32'hFFABFFA8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1301  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [4]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I3(rxreset322),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [36]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<36> )

  );
  LUT5 #(
    .INIT ( 32'hFFABFFA8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1331  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [7]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I3(rxreset322),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [39]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<39> )

  );
  LUT5 #(
    .INIT ( 32'hFFABFFA8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1341  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [35]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I3(rxreset322),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<3> )

  );
  LUT5 #(
    .INIT ( 32'hFFABFFA8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1451  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [36]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I3(rxreset322),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [4]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<4> )

  );
  LUT5 #(
    .INIT ( 32'hFFABFFA8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1521  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [24]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I3(rxreset322),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [56]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<56> )

  );
  LUT5 #(
    .INIT ( 32'hFFABFFA8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1621  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_delay [39]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I3(rxreset322),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/data_pipe [7]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_data_out[63]_GND_34_o_mux_31_OUT<7> )

  );
  LUT5 #(
    .INIT ( 32'hFFABFFA8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT51  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe [0]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I3(rxreset322),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/ctrl_pipe [4]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/fifo_ctrl_out[7]_GND_34_o_mux_32_OUT<4> )

  );
  LUT4 #(
    .INIT ( 16'h0008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n10781  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/_n1078 )
  );
  LUT6 #(
    .INIT ( 64'h1111111011110100 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1312  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [37]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [5]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<37> )

  );
  LUT6 #(
    .INIT ( 64'h1111111011110100 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1321  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [38]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [6]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<38> )

  );
  LUT6 #(
    .INIT ( 64'h1111111011110100 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1381  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [43]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [11]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<43> )

  );
  LUT6 #(
    .INIT ( 64'h1111111011110100 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1391  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [44]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [12]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<44> )

  );
  LUT6 #(
    .INIT ( 64'h1111111011110100 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1401  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [45]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [13]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<45> )

  );
  LUT6 #(
    .INIT ( 64'h1111111011110100 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1411  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [46]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [14]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<46> )

  );
  LUT6 #(
    .INIT ( 64'h1111111011110100 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1421  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [47]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [15]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<47> )

  );
  LUT6 #(
    .INIT ( 64'h1111111011110100 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1471  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [51]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [19]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<51> )

  );
  LUT6 #(
    .INIT ( 64'h1111111011110100 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1481  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [52]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [20]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<52> )

  );
  LUT6 #(
    .INIT ( 64'h1111111011110100 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1491  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [53]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [21]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<53> )

  );
  LUT6 #(
    .INIT ( 64'h1111111011110100 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1501  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [54]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [22]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<54> )

  );
  LUT6 #(
    .INIT ( 64'h1111111011110100 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1511  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [55]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [23]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<55> )

  );
  LUT6 #(
    .INIT ( 64'h1111111011110100 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1551  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [59]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [27]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<59> )

  );
  LUT6 #(
    .INIT ( 64'h1111111011110100 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1571  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [60]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [28]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<60> )

  );
  LUT6 #(
    .INIT ( 64'h1111111011110100 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1581  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [61]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [29]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<61> )

  );
  LUT6 #(
    .INIT ( 64'h1111111011110100 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1591  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [62]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [30]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<62> )

  );
  LUT6 #(
    .INIT ( 64'h1111111011110100 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1601  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [63]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [31]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<63> )

  );
  LUT6 #(
    .INIT ( 64'h5555555155555540 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT61  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [65]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o )
,
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [69]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_in[7]_GND_39_o_mux_22_OUT<5> )

  );
  LUT6 #(
    .INIT ( 64'h5555555155555540 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT71  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [66]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o )
,
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [70]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_in[7]_GND_39_o_mux_22_OUT<6> )

  );
  LUT6 #(
    .INIT ( 64'h5555555155555540 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT81  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [67]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o )
,
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [71]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_in[7]_GND_39_o_mux_22_OUT<7> )

  );
  LUT6 #(
    .INIT ( 64'h5555555155555540 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1271  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [1]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o )
,
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [33]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<33> )

  );
  LUT6 #(
    .INIT ( 64'h5555555155555540 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1361  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [9]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o )
,
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [41]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<41> )

  );
  LUT6 #(
    .INIT ( 64'h5555555155555540 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1371  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [10]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o )
,
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [42]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<42> )

  );
  LUT6 #(
    .INIT ( 64'h5555555155555540 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1441  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [17]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o )
,
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [49]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<49> )

  );
  LUT6 #(
    .INIT ( 64'h5555555155555540 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1461  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [18]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o )
,
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [50]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<50> )

  );
  LUT6 #(
    .INIT ( 64'h5555555155555540 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1531  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [25]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o )
,
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [57]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<57> )

  );
  LUT6 #(
    .INIT ( 64'h5555555155555540 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1541  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [26]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o )
,
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [58]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<58> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFFFFFD8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT51  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [64]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [68]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_in[7]_GND_39_o_mux_22_OUT<4> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFFFFFD8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1282  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [34]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[1]_PWR_41_o_equal_19_o )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<34> )

  );
  LUT6 #(
    .INIT ( 64'h0000040004000400 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/_n0120_inv1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4227 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4510 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_cnt [4]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/_n0120_inv )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFF44404044 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/_n0210_inv1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/full_int_3072 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3_2877 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd2_2878 ),
    .I5(rxreset322),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/_n0210_inv )
  );
  LUT6 #(
    .INIT ( 64'h5555400040004000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT142  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q [7]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q [7]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode1 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT141_5206 )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_54_o<15>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_54_o )
  );
  LUT6 #(
    .INIT ( 64'h0001000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_PWR_46_o_equal_56_o<15>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode11_5302 ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode12_5303 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_PWR_46_o_equal_56_o )
  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_47_o<15>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_47_o )
  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_51_o<15>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_51_o )
  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_53_o<15>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_53_o )
  );
  LUT5 #(
    .INIT ( 32'h00800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT152  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT15_5241 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT151_5242 )

  );
  LUT5 #(
    .INIT ( 32'h00800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT162  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT16_5255 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT161_5256 )

  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT168  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [16]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I3
(\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15/q_0 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [17]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_35_o<15>1_1724 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT167_5262 )

  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT56_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[4] ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out1411 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[15]_PWR_23_o_equal_102_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[2] ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[3] ),
    .O(N390)
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFBFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_invalid_cnt[4]_GND_26_o_mux_33_OUT11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_1_4221 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/signal_ok_reg_4222 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3_4394 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2_4393 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1_4422 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt[4]_GND_26_o_mux_33_OUT<0> )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFBFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_cnt[6]_GND_26_o_mux_32_OUT11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_1_4221 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/signal_ok_reg_4222 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3_4394 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd2_4393 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd1_4422 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt[6]_GND_26_o_mux_32_OUT<0> )
  );
  LUT6 #(
    .INIT ( 64'h6AAAAAAAAAAAAAAA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcount_block_count_xor<5>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [5]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [4]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [3]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Result [5])
  );
  LUT5 #(
    .INIT ( 32'h6AAAAAAA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcount_block_count_xor<4>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [4]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [3]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Result [4])
  );
  LUT4 #(
    .INIT ( 16'h6AAA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcount_block_count_xor<3>12  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Result [3])
  );
  LUT6 #(
    .INIT ( 64'h0001000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o )
  );
  LUT4 #(
    .INIT ( 16'h0008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[5]_AND_66_o1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n09151_3483 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [6]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [5]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [4]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[5]_AND_66_o )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFFFFFA2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>32  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_445_o<7>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [2]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_448_o ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>3 )
  );
  LUT6 #(
    .INIT ( 64'h11155555FFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT112  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1141 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[7]_tx_xgmii_data_reg1[7]_OR_155_o_3589 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_166_o ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_tx_xgmii_data_reg1[39]_OR_153_o_3588 )
,
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_GND_22_o_equal_165_o ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11411 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT111_5507 )
  );
  LUT4 #(
    .INIT ( 16'h5DFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11621  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out231 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1162 )
  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/re_rising1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_rnw ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/re_prev_2014 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[20]_GND_44_o_equal_101_o<20>1 )
,
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_addrdecode1 ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1726 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/re_rising )
  );
  LUT6 #(
    .INIT ( 64'hAAAAAAA2AAAAAAAA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_addr<16>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [4]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [2]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_read_AND_368_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [16])
  );
  LUT6 #(
    .INIT ( 64'hAAAAAAA2AAAAAAAA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_addr<17>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [4]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [2]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_read_AND_368_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_addr [17])
  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we11  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode11_5302 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_addrdecode1 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ),
    .I3(NlwRenamedSig_OI_pcs_resetout),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode12_5303 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_rnw ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we1 )
  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/Mmux_q[15]_d[15]_mux_3_OUT17  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q[15]_d[15]_mux_3_OUT<0> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/Mmux_q[15]_d[15]_mux_3_OUT21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [10]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q[15]_d[15]_mux_3_OUT<10> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/Mmux_q[15]_d[15]_mux_3_OUT31  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [11]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q[15]_d[15]_mux_3_OUT<11> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/Mmux_q[15]_d[15]_mux_3_OUT41  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [12]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q[15]_d[15]_mux_3_OUT<12> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/Mmux_q[15]_d[15]_mux_3_OUT51  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [13]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q[15]_d[15]_mux_3_OUT<13> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/Mmux_q[15]_d[15]_mux_3_OUT61  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [14]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q[15]_d[15]_mux_3_OUT<14> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/Mmux_q[15]_d[15]_mux_3_OUT71  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [15]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q[15]_d[15]_mux_3_OUT<15> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/Mmux_q[15]_d[15]_mux_3_OUT81  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q[15]_d[15]_mux_3_OUT<1> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/Mmux_q[15]_d[15]_mux_3_OUT91  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q[15]_d[15]_mux_3_OUT<2> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/Mmux_q[15]_d[15]_mux_3_OUT101  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q[15]_d[15]_mux_3_OUT<3> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/Mmux_q[15]_d[15]_mux_3_OUT111  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [4]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q[15]_d[15]_mux_3_OUT<4> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/Mmux_q[15]_d[15]_mux_3_OUT121  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q[15]_d[15]_mux_3_OUT<5> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/Mmux_q[15]_d[15]_mux_3_OUT131  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [6]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q[15]_d[15]_mux_3_OUT<6> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/Mmux_q[15]_d[15]_mux_3_OUT141  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [7]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q[15]_d[15]_mux_3_OUT<7> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/Mmux_q[15]_d[15]_mux_3_OUT151  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [8]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q[15]_d[15]_mux_3_OUT<8> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/Mmux_q[15]_d[15]_mux_3_OUT161  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [9]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_35_all/q[15]_d[15]_mux_3_OUT<9> )

  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/Mmux_q[15]_d[15]_mux_3_OUT17  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [0]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q[15]_d[15]_mux_3_OUT<0> )

  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/Mmux_q[15]_d[15]_mux_3_OUT21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [10]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q[15]_d[15]_mux_3_OUT<10> )

  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/Mmux_q[15]_d[15]_mux_3_OUT31  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [11]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q[15]_d[15]_mux_3_OUT<11> )

  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/Mmux_q[15]_d[15]_mux_3_OUT41  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [12]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q[15]_d[15]_mux_3_OUT<12> )

  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/Mmux_q[15]_d[15]_mux_3_OUT51  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [13]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q[15]_d[15]_mux_3_OUT<13> )

  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/Mmux_q[15]_d[15]_mux_3_OUT61  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [14]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q[15]_d[15]_mux_3_OUT<14> )

  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/Mmux_q[15]_d[15]_mux_3_OUT71  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [15]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q[15]_d[15]_mux_3_OUT<15> )

  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/Mmux_q[15]_d[15]_mux_3_OUT81  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q[15]_d[15]_mux_3_OUT<1> )

  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/Mmux_q[15]_d[15]_mux_3_OUT91  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q[15]_d[15]_mux_3_OUT<2> )

  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/Mmux_q[15]_d[15]_mux_3_OUT101  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q[15]_d[15]_mux_3_OUT<3> )

  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/Mmux_q[15]_d[15]_mux_3_OUT111  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [4]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q[15]_d[15]_mux_3_OUT<4> )

  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/Mmux_q[15]_d[15]_mux_3_OUT121  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [5]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q[15]_d[15]_mux_3_OUT<5> )

  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/Mmux_q[15]_d[15]_mux_3_OUT131  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [6]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q[15]_d[15]_mux_3_OUT<6> )

  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/Mmux_q[15]_d[15]_mux_3_OUT141  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [7]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q[15]_d[15]_mux_3_OUT<7> )

  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/Mmux_q[15]_d[15]_mux_3_OUT151  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [8]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q[15]_d[15]_mux_3_OUT<8> )

  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/Mmux_q[15]_d[15]_mux_3_OUT161  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [9]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_36_all/q[15]_d[15]_mux_3_OUT<9> )

  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/Mmux_q[15]_d[15]_mux_3_OUT17  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [0]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q[15]_d[15]_mux_3_OUT<0> )

  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/Mmux_q[15]_d[15]_mux_3_OUT21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [10]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q[15]_d[15]_mux_3_OUT<10> )

  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/Mmux_q[15]_d[15]_mux_3_OUT31  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [11]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q[15]_d[15]_mux_3_OUT<11> )

  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/Mmux_q[15]_d[15]_mux_3_OUT41  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [12]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q[15]_d[15]_mux_3_OUT<12> )

  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/Mmux_q[15]_d[15]_mux_3_OUT51  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [13]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q[15]_d[15]_mux_3_OUT<13> )

  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/Mmux_q[15]_d[15]_mux_3_OUT61  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [14]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q[15]_d[15]_mux_3_OUT<14> )

  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/Mmux_q[15]_d[15]_mux_3_OUT71  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [15]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q[15]_d[15]_mux_3_OUT<15> )

  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/Mmux_q[15]_d[15]_mux_3_OUT81  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q[15]_d[15]_mux_3_OUT<1> )

  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/Mmux_q[15]_d[15]_mux_3_OUT91  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q[15]_d[15]_mux_3_OUT<2> )

  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/Mmux_q[15]_d[15]_mux_3_OUT101  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q[15]_d[15]_mux_3_OUT<3> )

  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/Mmux_q[15]_d[15]_mux_3_OUT111  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [4]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q[15]_d[15]_mux_3_OUT<4> )

  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/Mmux_q[15]_d[15]_mux_3_OUT121  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [5]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q[15]_d[15]_mux_3_OUT<5> )

  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/Mmux_q[15]_d[15]_mux_3_OUT131  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [6]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q[15]_d[15]_mux_3_OUT<6> )

  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/Mmux_q[15]_d[15]_mux_3_OUT141  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [7]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q[15]_d[15]_mux_3_OUT<7> )

  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/Mmux_q[15]_d[15]_mux_3_OUT151  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [8]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q[15]_d[15]_mux_3_OUT<8> )

  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/Mmux_q[15]_d[15]_mux_3_OUT161  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [9]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_39_all/q[15]_d[15]_mux_3_OUT<9> )

  );
  LUT6 #(
    .INIT ( 64'hFEFEFEFFFEFEFEFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<33>11  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_448_o ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [2]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_445_o<7>1 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<33>1 )
  );
  LUT5 #(
    .INIT ( 32'hFEFFFEFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<41>11  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_448_o ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [1]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_445_o<7>1 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<41>1 )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFFFFFA2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<17>11  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_445_o<7>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [2]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_448_o ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_455_o ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<17>1 )
  );
  LUT3 #(
    .INIT ( 8'h6A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Maccum_tx_test_patt_seed_sel_xor<1>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count[6]_reduce_and_6_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Result [1])
  );
  LUT6 #(
    .INIT ( 64'h69C369693C963C3C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mxor_scr_comb<23>_xo<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [34]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [15]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [25]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [23])
  );
  LUT6 #(
    .INIT ( 64'h69C369693C963C3C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mxor_scr_comb<22>_xo<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [35]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [16]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [24]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [22])
  );
  LUT6 #(
    .INIT ( 64'h69C369693C963C3C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mxor_scr_comb<21>_xo<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [36]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [17]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [23]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [21])
  );
  LUT6 #(
    .INIT ( 64'h69C369693C963C3C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mxor_scr_comb<1>_xo<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [56]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [37]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [3]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [1])
  );
  LUT6 #(
    .INIT ( 64'h69C369693C963C3C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mxor_scr_comb<18>_xo<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [39]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [20]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [20]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [18])
  );
  LUT6 #(
    .INIT ( 64'h69C369693C963C3C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mxor_scr_comb<17>_xo<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [40]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [21]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [19]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [17])
  );
  LUT6 #(
    .INIT ( 64'h69C369693C963C3C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mxor_scr_comb<14>_xo<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [43]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [24]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [16]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [14])
  );
  LUT6 #(
    .INIT ( 64'h69C369693C963C3C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mxor_scr_comb<13>_xo<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [44]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [25]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [15]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [13])
  );
  LUT6 #(
    .INIT ( 64'h69C369693C963C3C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mxor_scr_comb<12>_xo<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [45]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [26]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [14]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [12])
  );
  LUT6 #(
    .INIT ( 64'h69C369693C963C3C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mxor_scr_comb<5>_xo<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [52]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [33]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [7]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [5])
  );
  LUT6 #(
    .INIT ( 64'h69C369693C963C3C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mxor_scr_comb<3>_xo<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [54]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [35]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [5]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [3])
  );
  LUT6 #(
    .INIT ( 64'h69C369693C963C3C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mxor_scr_comb<20>_xo<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [37]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [18]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [22]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [20])
  );
  LUT6 #(
    .INIT ( 64'h69C369693C963C3C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mxor_scr_comb<19>_xo<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [38]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [19]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [21]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [19])
  );
  LUT4 #(
    .INIT ( 16'h028A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0267_inv1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1341 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_cs ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rdack_1245 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [16]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/_n0267_inv )
  );
  LUT6 #(
    .INIT ( 64'h1111111011110100 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT131  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [11]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [43]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<11> )

  );
  LUT6 #(
    .INIT ( 64'h1111111011110100 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT141  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [12]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [44]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<12> )

  );
  LUT6 #(
    .INIT ( 64'h1111111011110100 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT151  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [13]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [45]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<13> )

  );
  LUT6 #(
    .INIT ( 64'h1111111011110100 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT165  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [14]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [46]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<14> )

  );
  LUT6 #(
    .INIT ( 64'h1111111011110100 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT171  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [15]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [47]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<15> )

  );
  LUT6 #(
    .INIT ( 64'h1111111011110100 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1112  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [19]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [51]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<19> )

  );
  LUT6 #(
    .INIT ( 64'h1111111011110100 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1131  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [20]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [52]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<20> )

  );
  LUT6 #(
    .INIT ( 64'h1111111011110100 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1141  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [21]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [53]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<21> )

  );
  LUT6 #(
    .INIT ( 64'h1111111011110100 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1151  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [22]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [54]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<22> )

  );
  LUT6 #(
    .INIT ( 64'h1111111011110100 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1161  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [23]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [55]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<23> )

  );
  LUT6 #(
    .INIT ( 64'h1111111011110100 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1201  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [27]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [59]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<27> )

  );
  LUT6 #(
    .INIT ( 64'h1111111011110100 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1211  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [28]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [60]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<28> )

  );
  LUT6 #(
    .INIT ( 64'h1111111011110100 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1221  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [29]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [61]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<29> )

  );
  LUT6 #(
    .INIT ( 64'h1111111011110100 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1241  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [30]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [62]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<30> )

  );
  LUT6 #(
    .INIT ( 64'h1111111011110100 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1251  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [31]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [63]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<31> )

  );
  LUT6 #(
    .INIT ( 64'h1111111011110100 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1561  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [5]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [37]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<5> )

  );
  LUT6 #(
    .INIT ( 64'h1111111011110100 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1611  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [6]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [38]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<6> )

  );
  LUT6 #(
    .INIT ( 64'h5555555155555540 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT21  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_delay [5]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o )
,
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [65]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_in[7]_GND_39_o_mux_22_OUT<1> )

  );
  LUT6 #(
    .INIT ( 64'h5555555155555540 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT31  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_delay [6]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o )
,
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [66]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_in[7]_GND_39_o_mux_22_OUT<2> )

  );
  LUT6 #(
    .INIT ( 64'h5555555155555540 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT41  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_delay [7]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o )
,
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [67]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_ctrl_in[7]_GND_39_o_mux_22_OUT<3> )

  );
  LUT6 #(
    .INIT ( 64'h5555555155555540 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT121  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [42]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o )
,
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [10]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<10> )

  );
  LUT6 #(
    .INIT ( 64'h5555555155555540 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT191  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [49]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o )
,
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [17]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<17> )

  );
  LUT6 #(
    .INIT ( 64'h5555555155555540 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1101  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [50]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o )
,
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [18]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<18> )

  );
  LUT6 #(
    .INIT ( 64'h5555555155555540 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1121  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [33]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o )
,
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<1> )

  );
  LUT6 #(
    .INIT ( 64'h5555555155555540 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1181  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [57]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o )
,
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [25]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<25> )

  );
  LUT6 #(
    .INIT ( 64'h5555555155555540 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1191  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [58]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o )
,
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [26]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<26> )

  );
  LUT6 #(
    .INIT ( 64'h5555555155555540 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1641  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [41]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o )
,
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [9]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<9> )

  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFFFFFD8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/Mmux_fifo_ctrl_in[7]_GND_39_o_mux_22_OUT1232  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/twist ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_delay [34]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/fifo_rd_data [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/jam_idle[0]_PWR_41_o_equal_16_o )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/reset_local_fault_OR_385_o ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/fifo_data_in[63]_GND_39_o_mux_21_OUT<2> )

  );
  LUT5 #(
    .INIT ( 32'h00010000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT121  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [4]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [7]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o<7>1_3480 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<1> )
  );
  LUT4 #(
    .INIT ( 16'h0008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [10]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<10> )
  );
  LUT4 #(
    .INIT ( 16'h0008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT71  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [15]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<15> )
  );
  LUT4 #(
    .INIT ( 16'h0008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT81  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [16]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<16> )
  );
  LUT4 #(
    .INIT ( 16'h0008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT91  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [17]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<17> )
  );
  LUT4 #(
    .INIT ( 16'h0008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [1]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<1> )
  );
  LUT4 #(
    .INIT ( 16'h0008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT151  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [22]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<22> )
  );
  LUT4 #(
    .INIT ( 16'h0008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT161  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [23]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<23> )
  );
  LUT4 #(
    .INIT ( 16'h0008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT171  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [24]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<24> )
  );
  LUT4 #(
    .INIT ( 16'h0008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT221  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [29]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<29> )
  );
  LUT4 #(
    .INIT ( 16'h0008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT241  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [30]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<30> )
  );
  LUT4 #(
    .INIT ( 16'h0008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT251  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [31]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<31> )
  );
  LUT4 #(
    .INIT ( 16'h0008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT301  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [36]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<36> )
  );
  LUT4 #(
    .INIT ( 16'h0008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT321  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [38]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<38> )
  );
  LUT4 #(
    .INIT ( 16'h0008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT311  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [37]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<37> )
  );
  LUT4 #(
    .INIT ( 16'h0008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT381  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [43]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<43> )
  );
  LUT4 #(
    .INIT ( 16'h0008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT391  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [44]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<44> )
  );
  LUT4 #(
    .INIT ( 16'h0008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT401  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [45]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<45> )
  );
  LUT4 #(
    .INIT ( 16'h0008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT461  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [50]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<50> )
  );
  LUT4 #(
    .INIT ( 16'h0008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT471  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [51]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<51> )
  );
  LUT4 #(
    .INIT ( 16'h0008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT481  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [52]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<52> )
  );
  LUT4 #(
    .INIT ( 16'h0008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT531  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [57]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<57> )
  );
  LUT4 #(
    .INIT ( 16'h0008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT551  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [59]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<59> )
  );
  LUT4 #(
    .INIT ( 16'h0008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT611  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [64]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<64> )
  );
  LUT4 #(
    .INIT ( 16'h0008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT621  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [65]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<65> )
  );
  LUT4 #(
    .INIT ( 16'h0008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT641  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [7]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<7> )
  );
  LUT4 #(
    .INIT ( 16'h0008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT661  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_encoded_data [9]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/Mmux_tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT121_4148 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out_t[65]_GND_23_o_mux_28_OUT<9> )
  );
  LUT6 #(
    .INIT ( 64'h69C369693C963C3C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT321  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [32]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [13]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [27]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT32_5528 )

  );
  LUT6 #(
    .INIT ( 64'h69C369693C963C3C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT311  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [31]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [12]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [28]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT31_5529 )

  );
  LUT6 #(
    .INIT ( 64'h69C369693C963C3C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT301  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [30]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [11]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [29]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT30 )

  );
  LUT6 #(
    .INIT ( 64'h69C369693C963C3C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT291  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [29]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [10]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [30]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT29 )

  );
  LUT6 #(
    .INIT ( 64'h69C369693C963C3C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT281  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [9]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [28]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [31]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT28 )

  );
  LUT6 #(
    .INIT ( 64'h69C369693C963C3C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT271  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [8]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [27]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [32]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT27 )

  );
  LUT6 #(
    .INIT ( 64'h69C369693C963C3C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT261  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [7]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [26]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [33]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT26 )

  );
  LUT6 #(
    .INIT ( 64'h69C369693C963C3C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT251  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [6]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [25]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [34]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT25 )

  );
  LUT6 #(
    .INIT ( 64'h69C369693C963C3C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT241  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [24]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [35]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT24 )

  );
  LUT6 #(
    .INIT ( 64'h69C369693C963C3C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT221  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [4]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [23]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [36]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT22_5539 )

  );
  LUT6 #(
    .INIT ( 64'h69C369693C963C3C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT211  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [22]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [37]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT21_5540 )

  );
  LUT6 #(
    .INIT ( 64'h69C369693C963C3C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT201  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [21]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [38]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT20 )

  );
  LUT6 #(
    .INIT ( 64'h69C369693C963C3C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT191  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [20]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [39]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT19 )

  );
  LUT6 #(
    .INIT ( 64'h69C369693C963C3C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT181  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [19]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [40]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT18 )

  );
  LUT2 #(
    .INIT ( 4'h4 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rnw_inv1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rnw_inv )
  );
  LUT4 #(
    .INIT ( 16'hAEA2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/Mmux_pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT17  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count [0]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT<0> )
  );
  LUT4 #(
    .INIT ( 16'hAEA2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/Mmux_pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [10]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count [10]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT<10> )

  );
  LUT4 #(
    .INIT ( 16'hAEA2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/Mmux_pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT31  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [11]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count [11]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT<11> )

  );
  LUT4 #(
    .INIT ( 16'hAEA2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/Mmux_pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT41  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [12]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count [12]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT<12> )

  );
  LUT4 #(
    .INIT ( 16'hAEA2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/Mmux_pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT51  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [13]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count [13]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT<13> )

  );
  LUT4 #(
    .INIT ( 16'hAEA2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/Mmux_pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT61  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [14]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count [14]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT<14> )

  );
  LUT4 #(
    .INIT ( 16'hAEA2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/Mmux_pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT71  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [15]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count [15]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT<15> )

  );
  LUT4 #(
    .INIT ( 16'hAEA2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/Mmux_pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT81  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT<1> )
  );
  LUT4 #(
    .INIT ( 16'hAEA2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/Mmux_pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT91  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT<2> )
  );
  LUT4 #(
    .INIT ( 16'hAEA2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/Mmux_pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT101  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT<3> )
  );
  LUT4 #(
    .INIT ( 16'hAEA2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/Mmux_pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT111  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [4]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count [4]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT<4> )
  );
  LUT4 #(
    .INIT ( 16'hAEA2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/Mmux_pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT121  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [5]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count [5]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT<5> )
  );
  LUT4 #(
    .INIT ( 16'hAEA2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/Mmux_pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT131  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [6]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count [6]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT<6> )
  );
  LUT4 #(
    .INIT ( 16'hAEA2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/Mmux_pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT141  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [7]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count [7]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT<7> )
  );
  LUT4 #(
    .INIT ( 16'hAEA2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/Mmux_pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT151  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [8]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count [8]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT<8> )
  );
  LUT4 #(
    .INIT ( 16'hAEA2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/Mmux_pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT161  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [9]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/prbs31_err_count [9]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/pcs_test_pattern_error_count[15]_rxprbs31_err_count[15]_mux_8_OUT<9> )
  );
  LUT6 #(
    .INIT ( 64'hAAABABAAAAA8A8AA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/Mmux_mgmt_rddata17  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1673 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [0])
  );
  LUT6 #(
    .INIT ( 64'hAAABABAAAAA8A8AA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/Mmux_mgmt_rddata21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out [10]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1673 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [10]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [10])
  );
  LUT6 #(
    .INIT ( 64'hAAABABAAAAA8A8AA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/Mmux_mgmt_rddata31  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out [11]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1673 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [11]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [11])
  );
  LUT6 #(
    .INIT ( 64'hAAABABAAAAA8A8AA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/Mmux_mgmt_rddata41  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out [12]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1673 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [12]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [12])
  );
  LUT6 #(
    .INIT ( 64'hAAABABAAAAA8A8AA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/Mmux_mgmt_rddata51  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out [13]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1673 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [13]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [13])
  );
  LUT6 #(
    .INIT ( 64'hAAABABAAAAA8A8AA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/Mmux_mgmt_rddata61  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out [14]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1673 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [14]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [14])
  );
  LUT6 #(
    .INIT ( 64'hAAABABAAAAA8A8AA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/Mmux_mgmt_rddata71  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out [15]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1673 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [15]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [15])
  );
  LUT6 #(
    .INIT ( 64'hAAABABAAAAA8A8AA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/Mmux_mgmt_rddata81  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1673 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [1])
  );
  LUT6 #(
    .INIT ( 64'hAAABABAAAAA8A8AA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/Mmux_mgmt_rddata91  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1673 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [2])
  );
  LUT6 #(
    .INIT ( 64'hAAABABAAAAA8A8AA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/Mmux_mgmt_rddata101  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1673 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [3]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [3])
  );
  LUT6 #(
    .INIT ( 64'hAAABABAAAAA8A8AA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/Mmux_mgmt_rddata111  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out [4]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1673 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [4]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [4])
  );
  LUT6 #(
    .INIT ( 64'hAAABABAAAAA8A8AA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/Mmux_mgmt_rddata121  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out [5]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1673 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [5]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [5])
  );
  LUT6 #(
    .INIT ( 64'hAAABABAAAAA8A8AA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/Mmux_mgmt_rddata131  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out [6]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1673 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [6]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [6])
  );
  LUT6 #(
    .INIT ( 64'hAAABABAAAAA8A8AA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/Mmux_mgmt_rddata141  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out [7]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1673 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [7]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [7])
  );
  LUT6 #(
    .INIT ( 64'hAAABABAAAAA8A8AA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/Mmux_mgmt_rddata151  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out [8]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1673 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [8]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [8])
  );
  LUT6 #(
    .INIT ( 64'hAAABABAAAAA8A8AA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/Mmux_mgmt_rddata161  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rddata_out [9]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1673 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [9]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rddata [9])
  );
  LUT3 #(
    .INIT ( 8'h10 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/Mmux_q[5]_GND_50_o_mux_3_OUT11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I1(reset),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [0]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/q[5]_GND_50_o_mux_3_OUT<0> )

  );
  LUT3 #(
    .INIT ( 8'h10 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/Mmux_q[5]_GND_50_o_mux_3_OUT21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I1(reset),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/q[5]_GND_50_o_mux_3_OUT<1> )

  );
  LUT3 #(
    .INIT ( 8'h10 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/Mmux_q[5]_GND_50_o_mux_3_OUT31  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I1(reset),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/q[5]_GND_50_o_mux_3_OUT<2> )

  );
  LUT3 #(
    .INIT ( 8'h10 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/Mmux_q[5]_GND_50_o_mux_3_OUT41  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I1(reset),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/q[5]_GND_50_o_mux_3_OUT<3> )

  );
  LUT3 #(
    .INIT ( 8'h10 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/Mmux_q[5]_GND_50_o_mux_3_OUT51  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I1(reset),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [4]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/q[5]_GND_50_o_mux_3_OUT<4> )

  );
  LUT3 #(
    .INIT ( 8'h10 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/Mmux_q[5]_GND_50_o_mux_3_OUT61  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I1(reset),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [5]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_13_8/q[5]_GND_50_o_mux_3_OUT<5> )

  );
  LUT3 #(
    .INIT ( 8'h10 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/Mmux_q[7]_GND_51_o_mux_3_OUT11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I1(reset),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [0]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q[7]_GND_51_o_mux_3_OUT<0> )

  );
  LUT3 #(
    .INIT ( 8'h10 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/Mmux_q[7]_GND_51_o_mux_3_OUT21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I1(reset),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q[7]_GND_51_o_mux_3_OUT<1> )

  );
  LUT3 #(
    .INIT ( 8'h10 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/Mmux_q[7]_GND_51_o_mux_3_OUT31  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I1(reset),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q[7]_GND_51_o_mux_3_OUT<2> )

  );
  LUT3 #(
    .INIT ( 8'h10 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/Mmux_q[7]_GND_51_o_mux_3_OUT41  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I1(reset),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q[7]_GND_51_o_mux_3_OUT<3> )

  );
  LUT3 #(
    .INIT ( 8'h10 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/Mmux_q[7]_GND_51_o_mux_3_OUT51  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I1(reset),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [4]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q[7]_GND_51_o_mux_3_OUT<4> )

  );
  LUT3 #(
    .INIT ( 8'h10 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/Mmux_q[7]_GND_51_o_mux_3_OUT61  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I1(reset),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [5]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q[7]_GND_51_o_mux_3_OUT<5> )

  );
  LUT3 #(
    .INIT ( 8'h10 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/Mmux_q[7]_GND_51_o_mux_3_OUT71  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I1(reset),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [6]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q[7]_GND_51_o_mux_3_OUT<6> )

  );
  LUT3 #(
    .INIT ( 8'h10 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/Mmux_q[7]_GND_51_o_mux_3_OUT81  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I1(reset),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [7]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q[7]_GND_51_o_mux_3_OUT<7> )

  );
  LUT3 #(
    .INIT ( 8'h10 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/Mmux_q[15]_GND_55_o_mux_3_OUT17  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I1(reset),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count [0]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q[15]_GND_55_o_mux_3_OUT<0> )

  );
  LUT3 #(
    .INIT ( 8'h10 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/Mmux_q[15]_GND_55_o_mux_3_OUT21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I1(reset),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count [10]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q[15]_GND_55_o_mux_3_OUT<10> )

  );
  LUT3 #(
    .INIT ( 8'h10 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/Mmux_q[15]_GND_55_o_mux_3_OUT31  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I1(reset),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count [11]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q[15]_GND_55_o_mux_3_OUT<11> )

  );
  LUT3 #(
    .INIT ( 8'h10 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/Mmux_q[15]_GND_55_o_mux_3_OUT41  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I1(reset),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count [12]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q[15]_GND_55_o_mux_3_OUT<12> )

  );
  LUT3 #(
    .INIT ( 8'h10 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/Mmux_q[15]_GND_55_o_mux_3_OUT51  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I1(reset),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count [13]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q[15]_GND_55_o_mux_3_OUT<13> )

  );
  LUT3 #(
    .INIT ( 8'h10 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/Mmux_q[15]_GND_55_o_mux_3_OUT61  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I1(reset),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count [14]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q[15]_GND_55_o_mux_3_OUT<14> )

  );
  LUT3 #(
    .INIT ( 8'h10 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/Mmux_q[15]_GND_55_o_mux_3_OUT71  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I1(reset),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count [15]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q[15]_GND_55_o_mux_3_OUT<15> )

  );
  LUT3 #(
    .INIT ( 8'h10 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/Mmux_q[15]_GND_55_o_mux_3_OUT81  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I1(reset),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q[15]_GND_55_o_mux_3_OUT<1> )

  );
  LUT3 #(
    .INIT ( 8'h10 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/Mmux_q[15]_GND_55_o_mux_3_OUT91  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I1(reset),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q[15]_GND_55_o_mux_3_OUT<2> )

  );
  LUT3 #(
    .INIT ( 8'h10 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/Mmux_q[15]_GND_55_o_mux_3_OUT101  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I1(reset),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q[15]_GND_55_o_mux_3_OUT<3> )

  );
  LUT3 #(
    .INIT ( 8'h10 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/Mmux_q[15]_GND_55_o_mux_3_OUT111  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I1(reset),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count [4]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q[15]_GND_55_o_mux_3_OUT<4> )

  );
  LUT3 #(
    .INIT ( 8'h10 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/Mmux_q[15]_GND_55_o_mux_3_OUT121  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I1(reset),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count [5]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q[15]_GND_55_o_mux_3_OUT<5> )

  );
  LUT3 #(
    .INIT ( 8'h10 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/Mmux_q[15]_GND_55_o_mux_3_OUT131  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I1(reset),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count [6]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q[15]_GND_55_o_mux_3_OUT<6> )

  );
  LUT3 #(
    .INIT ( 8'h10 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/Mmux_q[15]_GND_55_o_mux_3_OUT141  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I1(reset),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count [7]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q[15]_GND_55_o_mux_3_OUT<7> )

  );
  LUT3 #(
    .INIT ( 8'h10 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/Mmux_q[15]_GND_55_o_mux_3_OUT151  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I1(reset),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count [8]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q[15]_GND_55_o_mux_3_OUT<8> )

  );
  LUT3 #(
    .INIT ( 8'h10 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/Mmux_q[15]_GND_55_o_mux_3_OUT161  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I1(reset),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/prbs_err_count [9]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q[15]_GND_55_o_mux_3_OUT<9> )

  );
  LUT3 #(
    .INIT ( 8'h14 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Mmux_rd_nextgray[3]_PWR_39_o_mux_19_OUT21  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_nextgray[3]_PWR_39_o_mux_19_OUT<1> )

  );
  LUT3 #(
    .INIT ( 8'h14 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Mmux_rd_nextgray[3]_PWR_39_o_mux_19_OUT31  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_nextgray[3]_PWR_39_o_mux_19_OUT<2> )

  );
  LUT6 #(
    .INIT ( 64'h6AAAAAAAAAAAAAAA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mcount_block_count_xor<5>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count [5]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count [4]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Result [5])
  );
  LUT6 #(
    .INIT ( 64'h1511151115411441 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd2-In1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd2_4150 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd3_4151 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/state_FSM_FFd1_4149 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/_n0043 [58])
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFF15551515 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mcount_bit_count_eqn_01  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3_1497 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2_1496 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/n0027 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1498 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count_load_value [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Mcount_bit_count_eqn_0 )
  );
  LUT6 #(
    .INIT ( 64'h0000000000000069 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<11>  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [23]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [62]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [4]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [63]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [64]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [65]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcompar_rx_66_enc[65]_expected_data[63]_not_equal_7_o_lut<11>_4586 )

  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFF00000800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<40>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [6]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_304_o<7>1 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [4]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [5]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<39>2 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<40>1 )
  );
  LUT5 #(
    .INIT ( 32'h82D7FFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4510 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_done_INV_125_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3-In1_5565 )
  );
  LUT6 #(
    .INIT ( 64'h0000000000009600 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o8  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [57]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [38]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [7]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [3]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [6]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o8_5652 )
  );
  LUT6 #(
    .INIT ( 64'h0000009600000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o9  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [56]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [37]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [7]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [6]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T_valid_control_T_AND_117_o9_5653 )
  );
  LUT6 #(
    .INIT ( 64'hFF96FFFFFFFF69FF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/valid_control<3>_SW2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [35]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/pcs_descramble_i/descr_reg [54]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [5]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [6]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [4]),
    .O(N504)
  );
  LUT6 #(
    .INIT ( 64'h0800000008000800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_8_re1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode2 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_8_re )
  );
  LUT6 #(
    .INIT ( 64'h0800000008000800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_1_re1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode2 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_1_re )
  );
  LUT6 #(
    .INIT ( 64'hAAEAEAEA00404040 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT5221  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[2]_AND_57_o )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n09151_3483 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_PWR_23_o_equal_185_o2 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_126_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out1411 ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[31]_PWR_23_o_equal_118_o_mmx_out ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT522 )
  );
  LUT6 #(
    .INIT ( 64'h0404040004400400 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT139  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/_n0398 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT137_5204 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1673 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [6])
  );
  LUT6 #(
    .INIT ( 64'h0010001000100000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT120  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [19]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [18]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [20]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT129_5293 )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT18_5286 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [0])
  );
  LUT6 #(
    .INIT ( 64'h0010001000100000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT810  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [19]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [18]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [20]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT88_5301 )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT8 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [1])
  );
  LUT4 #(
    .INIT ( 16'h4555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/next_state [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_next_state1 ),
    .O(N366)
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFAAAA0020 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/_n0099_inv1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4510 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_done_INV_125_o ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4227 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/_n0099_inv )
  );
  LUT5 #(
    .INIT ( 32'h77FF45FF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT2321  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [1]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[31]_PWR_23_o_equal_118_o_mmx_out ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out231 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT232 )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFF80808000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT81  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out231 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [0]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[15]_PWR_23_o_equal_102_o_mmx_out ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT143_3443 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT8 )
  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15_we1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode2 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15_we )
  );
  LUT6 #(
    .INIT ( 64'h0010001000100000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT58  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [19]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [18]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [20]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT56_5269 )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT5 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [13])
  );
  LUT6 #(
    .INIT ( 64'h0202020002000200 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT13  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [16]),
    .I1
(\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15/q_0 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [17]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT17_5285 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_42_o ),
    .I5(pma_pmd_type[0]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT18_5286 )

  );
  LUT5 #(
    .INIT ( 32'h00800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1174  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1141 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11411 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_tx_xgmii_data_reg1[39]_OR_153_o_3588 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_166_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[3]_reduce_and_158_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1173 )
  );
  LUT6 #(
    .INIT ( 64'h5540404000404040 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1176  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[2]_AND_57_o )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[4]_AND_64_o )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[47]_PWR_23_o_equal_134_o_mmx_out ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n09151_3483 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_PWR_23_o_equal_185_o2 ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_126_o_mmx_out1 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1175 )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFAAAAAA80 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT19_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c2 [2]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o<7>1 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o<7>1 ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_445_o ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>2 ),
    .O(N166)
  );
  LUT6 #(
    .INIT ( 64'h0001010155555555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT18_SW0  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>2 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_445_o ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o<7>1 ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o<7>1 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c2 [1]),
    .O(N176)
  );
  LUT6 #(
    .INIT ( 64'h0001010155555555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT20_SW0  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>2 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_445_o ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o<7>1 ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o<7>1 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c2 [3]),
    .O(N178)
  );
  LUT6 #(
    .INIT ( 64'h0001010155555555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT21_SW0  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>2 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_445_o ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o<7>1 ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o<7>1 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c2 [4]),
    .O(N180)
  );
  LUT5 #(
    .INIT ( 32'hFFFFFFFD ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_PWR_32_o_c3[6]_mux_228_OUT51  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/c3[6]_GND_30_o_equal_62_o<6>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [33]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [35]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [34]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_66_enc [32]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/PWR_32_o_c3[6]_mux_228_OUT<4> )
  );
  LUT4 #(
    .INIT ( 16'hD580 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3-In3  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3-In2_5314 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/status [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3_2877 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3-In )
  );
  LUT6 #(
    .INIT ( 64'h66F6FFFF0090FFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3-In2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_66_raw [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[0].synch_inst/d1_d_MUX_806_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_invalid_cnt [4]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3-In1_5561 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/state_FSM_FFd3-In2_5562 )
  );
  LUT6 #(
    .INIT ( 64'h0010001000100000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT911  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [19]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [18]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [20]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT99_5187 )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT98_5186 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [2])
  );
  LUT6 #(
    .INIT ( 64'h0404040004400400 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT129  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/_n0398 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT127_5234 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1673 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [5])
  );
  LUT6 #(
    .INIT ( 64'h0010001000100000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT169  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [19]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [18]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [20]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT167_5262 )
,
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT166_5261 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [9])
  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT78  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [19]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [16]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [18]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [20]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT76_5276 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/GND_44_o_GND_44_o_mux_65_OUT [15])
  );
  LUT5 #(
    .INIT ( 32'hFAFA2AAA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1-In1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/status [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_idle [1]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/Mmux_fifo_ctrl_out[7]_GND_34_o_mux_32_OUT1110 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1-In )
  );
  LUT5 #(
    .INIT ( 32'h28888888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_cnt[6]_GND_26_o_mux_32_OUT41  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_cnt[6]_GND_26_o_mux_32_OUT22 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt[6]_GND_26_o_mux_32_OUT<3> )
  );
  LUT6 #(
    .INIT ( 64'h2888888888888888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_cnt[6]_GND_26_o_mux_32_OUT51  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/Mmux_sh_cnt[6]_GND_26_o_mux_32_OUT22 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [4]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt [3]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_block_lock_fsm_i/sh_cnt[6]_GND_26_o_mux_32_OUT<4> )
  );
  LUT5 #(
    .INIT ( 32'hFFFF2000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<28>11  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o<7>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [2]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o<7>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [1]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>111_3487 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<28>1 )
  );
  LUT5 #(
    .INIT ( 32'hFFFF2000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>12  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o<7>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [2]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o<7>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [1]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>11 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>1 )
  );
  LUT6 #(
    .INIT ( 64'h0001000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1712111  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [4]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_GND_22_o_equal_151_o1 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[7]_PWR_23_o_equal_182_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT171211 )
  );
  LUT6 #(
    .INIT ( 64'h2AAAAAAAAAAAAAAA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT311  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11411 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [4]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_GND_22_o_equal_151_o1 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT31 )
  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_GND_22_o_equal_165_o1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [4]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [6]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [7]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_PWR_23_o_equal_185_o3 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_GND_22_o_equal_165_o )
  );
  LUT6 #(
    .INIT ( 64'h8880080008000800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT102  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode11_5302 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode12_5303 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT10 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[20]_GND_44_o_equal_101_o<20>1 )
,
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT101_5221 )

  );
  LUT6 #(
    .INIT ( 64'h8880080008000800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT125  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode11_5302 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode12_5303 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT123_5230 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[20]_GND_44_o_equal_101_o<20>1 )
,
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [5]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT124_5231 )

  );
  LUT6 #(
    .INIT ( 64'h8880080008000800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT154  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode11_5302 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode12_5303 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT152_5243 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[20]_GND_44_o_equal_101_o<20>1 )
,
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [8]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT153_5244 )

  );
  LUT6 #(
    .INIT ( 64'h8880080008000800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT44  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode11_5302 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode12_5303 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT42_5250 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[20]_GND_44_o_equal_101_o<20>1 )
,
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [12]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT43_5251 )

  );
  LUT6 #(
    .INIT ( 64'h8880080008000800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT164  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode11_5302 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode12_5303 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT162_5257 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[20]_GND_44_o_equal_101_o<20>1 )
,
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [9]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT163_5258 )

  );
  LUT6 #(
    .INIT ( 64'h8880080008000800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT55  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode11_5302 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode12_5303 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT53_5266 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[20]_GND_44_o_equal_101_o<20>1 )
,
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [13]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT54_5267 )

  );
  LUT6 #(
    .INIT ( 64'h8880080008000800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT74  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode11_5302 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode12_5303 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT72_5272 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[20]_GND_44_o_equal_101_o<20>1 )
,
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [15]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT73_5273 )

  );
  LUT6 #(
    .INIT ( 64'h8880080008000800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT24  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode11_5302 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode12_5303 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT22_5279 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[20]_GND_44_o_equal_101_o<20>1 )
,
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [10]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT23_5280 )

  );
  LUT5 #(
    .INIT ( 32'hFFFF0888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT142  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n09151_3483 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_PWR_23_o_equal_185_o2 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out1411 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_126_o ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[2]_AND_57_o )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT141_5331 )
  );
  LUT6 #(
    .INIT ( 64'h51555555FFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT53  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT171211 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_GND_22_o_equal_165_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_166_o ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[7]_tx_xgmii_data_reg1[7]_OR_155_o_3589 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_tx_xgmii_data_reg1[39]_OR_153_o_3588 )
,
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT31 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT52_5410 )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFF8FFF8FFF8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>21  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o<7>1 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o<7>1 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_448_o ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>111_3487 )
,
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [5]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<10>2 )
  );
  LUT6 #(
    .INIT ( 64'h8888A88888888888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT28111  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/o0 [0]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_455_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [4]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [7]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o<7>1_3480 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT2811 )

  );
  LUT6 #(
    .INIT ( 64'h0001000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_GND_22_o_equal_181_o1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [5]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [6]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [7]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [4]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_PWR_23_o_equal_185_o3 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_GND_22_o_equal_181_o )
  );
  LUT5 #(
    .INIT ( 32'hFFF8FFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT110  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o<7>1 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o<7>1 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>11 )
,
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<0> )
  );
  LUT6 #(
    .INIT ( 64'h8880080008000800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT115  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode11_5302 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode12_5303 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT113_5216 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[20]_GND_44_o_equal_101_o<20>1 )
,
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [4]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT114_5217 )

  );
  LUT6 #(
    .INIT ( 64'h8880080008000800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT64  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode11_5302 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65520_addrdecode12_5303 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT62_5237 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[20]_GND_44_o_equal_101_o<20>1 )
,
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [14]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT63_5238 )

  );
  LUT6 #(
    .INIT ( 64'h011105553333FFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT33_SW0  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>111_3487 )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<31>2 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o<7>1 ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o<7>1 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d4 [5]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c4 [1]),
    .O(N94)
  );
  LUT6 #(
    .INIT ( 64'h011105553333FFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT35_SW0  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>111_3487 )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<31>2 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o<7>1 ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o<7>1 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d4 [6]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c4 [2]),
    .O(N96)
  );
  LUT6 #(
    .INIT ( 64'h011105553333FFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT36_SW0  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>111_3487 )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<31>2 ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o<7>1 ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o<7>1 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d4 [7]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c4 [3]),
    .O(N98)
  );
  LUT5 #(
    .INIT ( 32'h1555FFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT17_SW0  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<49>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [2]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_445_o<7>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c2 [0]),
    .O(N120)
  );
  LUT5 #(
    .INIT ( 32'h1555FFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT22_SW0  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<49>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [2]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_445_o<7>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c2 [5]),
    .O(N122)
  );
  LUT5 #(
    .INIT ( 32'h1555FFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT24_SW0  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<49>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [2]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_445_o<7>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c2 [6]),
    .O(N124)
  );
  LUT6 #(
    .INIT ( 64'h5555555544405555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT30  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d3 [2]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>31 )
,
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ),
    .I4(N128),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT2811 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<36> )
  );
  LUT6 #(
    .INIT ( 64'h5555555544405555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT31  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d3 [3]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>31 )
,
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ),
    .I4(N130),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT2811 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<37> )
  );
  LUT6 #(
    .INIT ( 64'h4444444055555555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT55  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c7 [0]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<28>1 ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_448_o ),
    .I5(N132),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<59> )
  );
  LUT6 #(
    .INIT ( 64'h4444444055555555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT61  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c7 [5]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<28>1 ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_448_o ),
    .I5(N134),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<64> )
  );
  LUT6 #(
    .INIT ( 64'h4444444055555555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT62  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c7 [6]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<28>1 ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_448_o ),
    .I5(N136),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<65> )
  );
  LUT5 #(
    .INIT ( 32'h55555545 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT52  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[3]_AND_61_o )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out231 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT51_5409 )
  );
  LUT4 #(
    .INIT ( 16'hEE0E ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_14/_n00141  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I1(reset),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_re ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_15/re_prev_1998 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_14/_n0014 )
  );
  LUT6 #(
    .INIT ( 64'hEAAAAAAAAAAAAAAA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/_n0012_inv1  (
    .I0(NlwRenamedSig_OI_pcs_resetout),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we1 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/_n0012_inv )
  );
  LUT5 #(
    .INIT ( 32'hFFFF4044 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [7]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o<7>1_3480 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [4]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_455_o ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>1 )
  );
  LUT6 #(
    .INIT ( 64'h55555155FFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT38_SW0  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [7]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [0]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o<7>1_3480 )
,
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [4]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d4 [1]),
    .O(N116)
  );
  LUT6 #(
    .INIT ( 64'h55555155FFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT39_SW0  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [7]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [0]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o<7>1_3480 )
,
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [4]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d4 [2]),
    .O(N118)
  );
  LUT5 #(
    .INIT ( 32'hFFFFFDFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT204  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [7]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [6]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_PWR_23_o_equal_185_o3 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [5]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT203_5485 )
  );
  LUT6 #(
    .INIT ( 64'h69C369693C963C3C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT171  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [18]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [41]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT17 )

  );
  LUT6 #(
    .INIT ( 64'h69C369693C963C3C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT151  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [16]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [43]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT15 )

  );
  LUT6 #(
    .INIT ( 64'h69C369693C963C3C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT131  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [14]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [4]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [45]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT13 )

  );
  LUT6 #(
    .INIT ( 64'h69C369693C963C3C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT101  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [12]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [6]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [47]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT10 )

  );
  LUT6 #(
    .INIT ( 64'hEBEBC369BEBE963C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr541  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [17]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/test_patt_sel_GND_24_o_equal_15_o_mmx_out ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [58]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [58])
  );
  LUT5 #(
    .INIT ( 32'h00000800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT61  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [16]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [17]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/_n0398 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT6 )
  );
  LUT4 #(
    .INIT ( 16'h0002 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT41  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [19]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [18]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [20]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT2 )
  );
  LUT5 #(
    .INIT ( 32'h00800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/Mmux_ipif_rddata_dclk17  (
    .I0(drp_drdy),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [33]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [32]),
    .I3(reset),
    .I4(drp_drpdo[0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [0])
  );
  LUT5 #(
    .INIT ( 32'h00800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/Mmux_ipif_rddata_dclk21  (
    .I0(drp_drdy),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [33]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [32]),
    .I3(reset),
    .I4(drp_drpdo[10]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [10])
  );
  LUT5 #(
    .INIT ( 32'h00800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/Mmux_ipif_rddata_dclk31  (
    .I0(drp_drdy),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [33]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [32]),
    .I3(reset),
    .I4(drp_drpdo[11]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [11])
  );
  LUT5 #(
    .INIT ( 32'h00800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/Mmux_ipif_rddata_dclk41  (
    .I0(drp_drdy),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [33]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [32]),
    .I3(reset),
    .I4(drp_drpdo[12]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [12])
  );
  LUT5 #(
    .INIT ( 32'h00800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/Mmux_ipif_rddata_dclk51  (
    .I0(drp_drdy),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [33]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [32]),
    .I3(reset),
    .I4(drp_drpdo[13]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [13])
  );
  LUT5 #(
    .INIT ( 32'h00800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/Mmux_ipif_rddata_dclk61  (
    .I0(drp_drdy),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [33]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [32]),
    .I3(reset),
    .I4(drp_drpdo[14]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [14])
  );
  LUT5 #(
    .INIT ( 32'h00800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/Mmux_ipif_rddata_dclk71  (
    .I0(drp_drdy),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [33]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [32]),
    .I3(reset),
    .I4(drp_drpdo[15]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [15])
  );
  LUT5 #(
    .INIT ( 32'h00800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/Mmux_ipif_rddata_dclk81  (
    .I0(drp_drdy),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [33]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [32]),
    .I3(reset),
    .I4(drp_drpdo[1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [1])
  );
  LUT5 #(
    .INIT ( 32'h00800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/Mmux_ipif_rddata_dclk91  (
    .I0(drp_drdy),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [33]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [32]),
    .I3(reset),
    .I4(drp_drpdo[2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [2])
  );
  LUT5 #(
    .INIT ( 32'h00800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/Mmux_ipif_rddata_dclk101  (
    .I0(drp_drdy),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [33]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [32]),
    .I3(reset),
    .I4(drp_drpdo[3]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [3])
  );
  LUT5 #(
    .INIT ( 32'h00800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/Mmux_ipif_rddata_dclk111  (
    .I0(drp_drdy),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [33]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [32]),
    .I3(reset),
    .I4(drp_drpdo[4]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [4])
  );
  LUT5 #(
    .INIT ( 32'h00800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/Mmux_ipif_rddata_dclk121  (
    .I0(drp_drdy),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [33]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [32]),
    .I3(reset),
    .I4(drp_drpdo[5]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [5])
  );
  LUT5 #(
    .INIT ( 32'h00800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/Mmux_ipif_rddata_dclk131  (
    .I0(drp_drdy),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [33]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [32]),
    .I3(reset),
    .I4(drp_drpdo[6]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [6])
  );
  LUT5 #(
    .INIT ( 32'h00800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/Mmux_ipif_rddata_dclk141  (
    .I0(drp_drdy),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [33]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [32]),
    .I3(reset),
    .I4(drp_drpdo[7]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [7])
  );
  LUT5 #(
    .INIT ( 32'h00800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/Mmux_ipif_rddata_dclk151  (
    .I0(drp_drdy),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [33]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [32]),
    .I3(reset),
    .I4(drp_drpdo[8]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [8])
  );
  LUT5 #(
    .INIT ( 32'h00800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/Mmux_ipif_rddata_dclk161  (
    .I0(drp_drdy),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [33]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/q [32]),
    .I3(reset),
    .I4(drp_drpdo[9]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/ipif_rddata_dclk [9])
  );
  LUT6 #(
    .INIT ( 64'h000100050003000F ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT31_SW1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_5_4973 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [47]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT2721 ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<24>3 ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<24>2 ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<24>1 ),
    .O(N640)
  );
  LUT6 #(
    .INIT ( 64'h4444040054555455 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT31  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [39]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_314_o ),
    .I5(N640),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<37> )
  );
  LUT5 #(
    .INIT ( 32'h0105030F ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT26_SW1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_0_4969 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [42]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<24>3 ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<24>2 ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<24>1 ),
    .O(N642)
  );
  LUT6 #(
    .INIT ( 64'h4444040054555455 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT26  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [34]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_314_o ),
    .I5(N642),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<32> )
  );
  LUT6 #(
    .INIT ( 64'h000100050003000F ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT273_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_1_4970 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [43]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT27 ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT2721 ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<24>2 ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<24>1 ),
    .O(N644)
  );
  LUT6 #(
    .INIT ( 64'h4444040054555455 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT273  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [35]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_314_o ),
    .I5(N644),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<33> )
  );
  LUT4 #(
    .INIT ( 16'h0057 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT37_SW1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [52]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_308_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_309_o ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<10>1 ),
    .O(N646)
  );
  LUT6 #(
    .INIT ( 64'h00AA000000FB00F3 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT37  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [44]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT351_4675 )
,
    .I5(N646),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<42> )
  );
  LUT6 #(
    .INIT ( 64'h7FFFFFFFFFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_PWR_23_o_equal_185_o111_SW1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [4]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [6]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [7]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[7]_tx_xgmii_data_reg1[7]_OR_155_o_3589 )
,
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[4] ),
    .O(N648)
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFDFFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_PWR_23_o_equal_185_o111  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out1411 ),
    .I1(N648),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [3]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [0]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_PWR_23_o_equal_185_o_mmx_out1 )
  );
  LUT6 #(
    .INIT ( 64'h101000101111FF11 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_8_10/q_0_rstpot1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I1(reset),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_8_10/q_0_1926 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_8_re ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_8_10/re_prev_1754 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_clk156_resyncs_i/resynch[2].synch_inst/q_549 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_8_10/q_0_rstpot1_5798 )
  );
  LUT5 #(
    .INIT ( 32'hFF808080 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT83_SW0  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1726 )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[20]_GND_44_o_equal_101_o<20>1 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_all/q [1]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_PWR_46_o_equal_60_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [1]),
    .O(N650)
  );
  LUT6 #(
    .INIT ( 64'hEAEAEAEAFFEAEAEA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT83  (
    .I0(N650),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_46_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [1]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_35_o<15>1_1724 )
,
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT82 )

  );
  LUT5 #(
    .INIT ( 32'h55F54404 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_8_11/q_0_rstpot1  (
    .I0
(\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15/q_0 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_8_11/q_0_1927 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_8_re ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_8_10/re_prev_1753 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/full_int_838 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_8_11/q_0_rstpot1_5797 )
  );
  LUT5 #(
    .INIT ( 32'h0808AA08 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_1_2/q_0_rstpot1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_5/d2_550 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_1_re ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_1_2/re_prev_1756 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_1_2/q_0_1960 ),
    .I4
(\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15/q_0 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_1_2/q_0_rstpot1_5799 )
  );
  LUT4 #(
    .INIT ( 16'hFEE8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_sync_extra_rstpot  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_2/q_3397 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_3/q_3396 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/psynch_1/q_3398 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_sync_extra_3395 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_sync_extra_rstpot_5792 )
  );
  LUT4 #(
    .INIT ( 16'hFEE8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_sync_extra_rstpot  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_2/q_3417 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_3/q_3416 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/psynch_1/q_3418 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_sync_extra_3415 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_sync_extra_rstpot_5793 )
  );
  LUT4 #(
    .INIT ( 16'hFEE8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_sync_extra_rstpot  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_2/q_3437 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_3/q_3436 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/psynch_1/q_3438 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_sync_extra_3435 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_sync_extra_rstpot_5794 )
  );
  LUT4 #(
    .INIT ( 16'h2262 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_1_glue_set  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_1_3432 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_count_inc_551 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_2_3434 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_1_glue_set_5683 )
  );
  LUT4 #(
    .INIT ( 16'h6222 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_3_glue_set  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_3_3433 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_2_3434 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_count_inc_551 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_3_glue_set_5684 )
  );
  LUT4 #(
    .INIT ( 16'h6222 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_2_glue_set  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_2_3434 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_1_3432 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/ber_count_inc_551 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_ber_counter_i/counter_2_glue_set_5685 )
  );
  LUT4 #(
    .INIT ( 16'hFFF8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/local_fault_rstpot  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/can_insert_rd ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/local_fault_3335 ),
    .I2(reset),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/empty_int_2483 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_insert_i/local_fault_rstpot_5791 )
  );
  LUT5 #(
    .INIT ( 32'hEFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/o4_0_rstpot_SW1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [37]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [33]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [34]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [35]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [36]),
    .O(N652)
  );
  LUT6 #(
    .INIT ( 64'hAAAAAAAEAAA2AAAA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/o4_0_rstpot  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/o4 [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [4]),
    .I2(N652),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [32]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [39]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [38]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/o4_0_rstpot_5789 )
  );
  LUT5 #(
    .INIT ( 32'hEFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/o0_0_rstpot_SW1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [5]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [4]),
    .O(N654)
  );
  LUT6 #(
    .INIT ( 64'hAAAAAAAEAAA2AAAA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/o0_0_rstpot  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/o0 [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [0]),
    .I2(N654),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [7]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg2 [6]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/o0_0_rstpot_5790 )
  );
  LUT3 #(
    .INIT ( 8'hFB ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/we_rstpot1_SW1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1_1495 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1498 ),
    .O(N656)
  );
  LUT6 #(
    .INIT ( 64'h1010101054101010 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/we_rstpot1  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdc_rising_1341 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/we_1362 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/opcode [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/n0027 ),
    .I5(N656),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/we_rstpot1_5796 )
  );
  LUT6 #(
    .INIT ( 64'h8000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o7_SW1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [50]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [51]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [52]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [53]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [54]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [55]),
    .O(N658)
  );
  LUT6 #(
    .INIT ( 64'h40FF404040404040 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o7  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [56]),
    .I1(N616),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [57]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [48]),
    .I4(N658),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [49]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o7_5383 )

  );
  LUT6 #(
    .INIT ( 64'h8000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o12_SW1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [4]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [5]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [6]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [7]),
    .O(N660)
  );
  LUT6 #(
    .INIT ( 64'h40FF404040404040 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o12  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [32]),
    .I1(N618),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [33]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [0]),
    .I4(N660),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o12_5384 )

  );
  LUT6 #(
    .INIT ( 64'hDFFFFFFFFFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o17_SW1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [12]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [8]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [13]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [14]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [15]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [9]),
    .O(N662)
  );
  LUT6 #(
    .INIT ( 64'h40FF404040404040 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o17  (
    .I0(N662),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [11]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [10]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [16]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [17]),
    .I5(N620),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o17_5385 )

  );
  LUT5 #(
    .INIT ( 32'h00000008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we )
  );
  LUT6 #(
    .INIT ( 64'h0000000000000002 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_35_o<15>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_35_o )
  );
  LUT6 #(
    .INIT ( 64'h0001000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_43_o<15>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_43_o )
  );
  LUT6 #(
    .INIT ( 64'h888888F888888888 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT32_SW1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c4 [0]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<28>1 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d4 [4]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [4]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [7]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o<7>1_3480 )
,
    .O(N664)
  );
  LUT6 #(
    .INIT ( 64'h5555555555554440 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT32  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/d3 [4]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_451_o ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>31 )
,
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<25>3_3486 )
,
    .I5(N664),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT<38> )
  );
  LUT4 #(
    .INIT ( 16'hFF08 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT11021  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_next_state1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/next_state [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_rx_ebuff_ctrl[7]_GND_31_o_mux_42_OUT1102 )
  );
  LUT6 #(
    .INIT ( 64'hEAAAAAAAAAAAAAAA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/pcs_clear_test_pattern_error_count_core1  (
    .I0(NlwRenamedSig_OI_pcs_resetout),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_rnw ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[20]_GND_44_o_equal_101_o<20>1 )
,
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_addrdecode1 ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1726 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clear_test_pattern_err_count )
  );
  LUT6 #(
    .INIT ( 64'hA2A2A2A2A3A2A2A2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>1111  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_445_o<7>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [0]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o<7>1 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>111_3487 )

  );
  LUT6 #(
    .INIT ( 64'hAAABABAAAAA8A8AA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/Mmux_mgmt_rdack11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rdack_1245 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1673 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [16]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rdack )
  );
  LUT3 #(
    .INIT ( 8'h20 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/Mmux_ipif_wrdata17  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [0])
  );
  LUT6 #(
    .INIT ( 64'h69C369693C963C3C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mxor_scr_comb<9>_xo<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [48]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [29]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [11]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [9])
  );
  LUT6 #(
    .INIT ( 64'h69C369693C963C3C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mxor_scr_comb<8>_xo<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [49]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [30]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [10]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [8])
  );
  LUT6 #(
    .INIT ( 64'h69C369693C963C3C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mxor_scr_comb<7>_xo<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [50]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [31]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [9]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [7])
  );
  LUT6 #(
    .INIT ( 64'h69C369693C963C3C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mxor_scr_comb<16>_xo<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [41]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [22]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [18]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [16])
  );
  LUT6 #(
    .INIT ( 64'h69C369693C963C3C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mxor_scr_comb<15>_xo<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [42]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [23]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [17]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [15])
  );
  LUT6 #(
    .INIT ( 64'h69C369693C963C3C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mxor_scr_comb<11>_xo<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [46]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [27]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [13]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [11])
  );
  LUT6 #(
    .INIT ( 64'h69C369693C963C3C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mxor_scr_comb<10>_xo<0>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [47]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [28]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [12]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [10])
  );
  LUT3 #(
    .INIT ( 8'h20 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/Mmux_ipif_wrdata21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [10]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [10])
  );
  LUT3 #(
    .INIT ( 8'h20 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/Mmux_ipif_wrdata31  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [11]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [11])
  );
  LUT3 #(
    .INIT ( 8'h20 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/Mmux_ipif_wrdata41  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [12]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [12])
  );
  LUT3 #(
    .INIT ( 8'h20 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/Mmux_ipif_wrdata51  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [13]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [13])
  );
  LUT3 #(
    .INIT ( 8'h20 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/Mmux_ipif_wrdata61  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [14]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [14])
  );
  LUT3 #(
    .INIT ( 8'h20 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/Mmux_ipif_wrdata71  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [15]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [15])
  );
  LUT3 #(
    .INIT ( 8'h20 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/Mmux_ipif_wrdata81  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [1])
  );
  LUT3 #(
    .INIT ( 8'h20 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/Mmux_ipif_wrdata91  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [2])
  );
  LUT3 #(
    .INIT ( 8'h20 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/Mmux_ipif_wrdata101  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [3]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [3])
  );
  LUT3 #(
    .INIT ( 8'h20 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/Mmux_ipif_wrdata111  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [4]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [4])
  );
  LUT3 #(
    .INIT ( 8'h20 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/Mmux_ipif_wrdata121  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [5]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [5])
  );
  LUT3 #(
    .INIT ( 8'h20 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/Mmux_ipif_wrdata131  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [6]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [6])
  );
  LUT3 #(
    .INIT ( 8'h20 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/Mmux_ipif_wrdata141  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [7]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [7])
  );
  LUT3 #(
    .INIT ( 8'h20 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/Mmux_ipif_wrdata151  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [8]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [8])
  );
  LUT3 #(
    .INIT ( 8'h20 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/Mmux_ipif_wrdata161  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [9]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ipif_wrdata [9])
  );
  LUT6 #(
    .INIT ( 64'hF9F9F9F9A9298909 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count_load_en1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd2_1496 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd3_1497 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd4_1498 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/n0027 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1-In1 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state_FSM_FFd1_1495 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/bit_count_load_en )
  );
  LUT5 #(
    .INIT ( 32'h00800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out221  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code52_5390 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [4]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [34]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o )
,
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out1411 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[7]_reduce_and_188_o )
  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out1412  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [3]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_data_reg1[7]_AND_40_o )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [26]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code42_5422 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[4] ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out1411 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out141 )
  );
  LUT5 #(
    .INIT ( 32'hFFFFFDFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT2111  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n09151_3483 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [4]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [5]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [6]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[55]_PWR_23_o_equal_142_o_mmx_out_3506 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT211 )
  );
  LUT5 #(
    .INIT ( 32'hFFFF8088 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>23  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o<7>1 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o<7>1 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [1]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>22_5405 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>2 )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFF00010000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>311  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [2]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o<7>1 ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_449_o<7>1_3474 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>31 )
  );
  LUT6 #(
    .INIT ( 64'h0001000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[3]_AND_61_o1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [7]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_PWR_23_o_equal_185_o2 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[3]_AND_61_o )
  );
  LUT5 #(
    .INIT ( 32'h00000008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_read_AND_368_o1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [5]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1361 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_read_AND_368_o )
  );
  LUT5 #(
    .INIT ( 32'h00000800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_we1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_we )
  );
  LUT5 #(
    .INIT ( 32'h00000800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_we1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_we )
  );
  LUT5 #(
    .INIT ( 32'h00000008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we )
  );
  LUT3 #(
    .INIT ( 8'h10 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_we1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I1(reset),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15_we ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_we )
  );
  LUT5 #(
    .INIT ( 32'hFFFF2000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<49>11  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o<7>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [2]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o<7>1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [1]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<49>1 )
  );
  LUT6 #(
    .INIT ( 64'h0001000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n09151  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [6]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [5]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [4]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n09151_3483 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[63]_PWR_23_o_equal_148_o ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n0915 )
  );
  LUT4 #(
    .INIT ( 16'h91A2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2-In11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1673 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/wrack_1244 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2-In1 )
  );
  LUT5 #(
    .INIT ( 32'hEFFFF7FF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_ctrl_out[7]_GND_30_o_mux_323_OUT6_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [6]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [4]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_306_o<7>1 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [5]),
    .O(N262)
  );
  LUT6 #(
    .INIT ( 64'h9696966996699696 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT551  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [20]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [39]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [20]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [59]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT55 )

  );
  LUT6 #(
    .INIT ( 64'h9696966996699696 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT541  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [38]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [19]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [21]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [60]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT54 )

  );
  LUT6 #(
    .INIT ( 64'h9696966996699696 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT451  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [37]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [18]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [22]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [61]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT45 )

  );
  LUT6 #(
    .INIT ( 64'h9696966996699696 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT41  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [26]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [6]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [45]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [14]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [53]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT4 )

  );
  LUT6 #(
    .INIT ( 64'h9696966996699696 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT341  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [17]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [36]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [23]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [62]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT34 )

  );
  LUT6 #(
    .INIT ( 64'h9696966996699696 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT31  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [25]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [44]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [15]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [54]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT3 )

  );
  LUT6 #(
    .INIT ( 64'h9696966996699696 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT231  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [22]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [54]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [35]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [5]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [63]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT23 )

  );
  LUT6 #(
    .INIT ( 64'h9696966996699696 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [24]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [4]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [43]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [16]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [55]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT2 )

  );
  LUT6 #(
    .INIT ( 64'h9696966996699696 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT161  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [37]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [17]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [56]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [3]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [42]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT16 )

  );
  LUT6 #(
    .INIT ( 64'h9696966996699696 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT141  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [35]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [15]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [54]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [5]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [44]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT14 )

  );
  LUT6 #(
    .INIT ( 64'h9696966996699696 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT121  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [15]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [4]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [34]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [25]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [64]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT12_5550 )

  );
  LUT6 #(
    .INIT ( 64'h9696966996699696 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT111  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [33]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [13]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [52]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [7]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [46]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT11_5551 )

  );
  LUT6 #(
    .INIT ( 64'h9696966996699696 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [24]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [52]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [33]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [7]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [65]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_scr_comb[6]_tx_test_patt_seed_sel[1]_mux_33_OUT1 )

  );
  LUT6 #(
    .INIT ( 64'h0440004004000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT271  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [5]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [6]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [4]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_312_o<7>1 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_310_o<7>1 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT27 )
  );
  LUT6 #(
    .INIT ( 64'h0440004004000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/out8_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [4]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [6]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [5]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_312_o<7>1 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_310_o<7>1 ),
    .O(N248)
  );
  LUT6 #(
    .INIT ( 64'hFFFFA7F7FFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_ctrl_out[7]_GND_30_o_mux_323_OUT3_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [5]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_304_o<7>1 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [6]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_310_o<7>1 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [4]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [3]),
    .O(N264)
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFBFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT177_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out231 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out141 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[23]_PWR_23_o_equal_110_o ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [1]),
    .O(N394)
  );
  LUT3 #(
    .INIT ( 8'h10 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/wrack_cs_AND_303_o1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/wrack_1244 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/wrack_cs_AND_303_o )
  );
  LUT5 #(
    .INIT ( 32'h88880008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11116_SW0_G  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out231 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11111_5335 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [1]),
    .O(N589)
  );
  LUT3 #(
    .INIT ( 8'hFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_error_block_count_OR_394_o1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_re ),
    .I2(reset),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_error_block_count_OR_394_o )
  );
  LUT3 #(
    .INIT ( 8'hFE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_395_o1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_re ),
    .I2(reset),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_reset_pcs_clear_test_pattern_error_count_OR_395_o )

  );
  LUT6 #(
    .INIT ( 64'hEBEBC369BEBE963C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr61  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [26]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [45]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [14]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [14])
  );
  LUT6 #(
    .INIT ( 64'hEBEBC369BEBE963C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr71  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [25]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [44]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [15]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [15])
  );
  LUT6 #(
    .INIT ( 64'hEBEBC369BEBE963C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr81  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [24]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [43]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [16]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [16])
  );
  LUT6 #(
    .INIT ( 64'hEBEBC369BEBE963C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr111  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [21]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [40]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [19]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [19])
  );
  LUT6 #(
    .INIT ( 64'hEBEBC369BEBE963C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr131  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [20]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [39]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [20]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [20])
  );
  LUT6 #(
    .INIT ( 64'hEBEBC369BEBE963C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr141  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [19]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [38]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [21]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [21])
  );
  LUT6 #(
    .INIT ( 64'h7007522525520770 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr151  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [18]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [37]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [22]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [22])
  );
  LUT6 #(
    .INIT ( 64'h7007522525520770 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr161  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [17]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [36]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [23]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [23])
  );
  LUT6 #(
    .INIT ( 64'h7007522525520770 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr171  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [16]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [35]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [24]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [24])
  );
  LUT6 #(
    .INIT ( 64'h7007522525520770 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr181  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [15]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [34]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [25]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [25])
  );
  LUT6 #(
    .INIT ( 64'h7007522525520770 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr341  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [37]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [56]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [3]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [3])
  );
  LUT6 #(
    .INIT ( 64'h7007522525520770 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr561  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [35]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [54]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [5]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [5])
  );
  LUT6 #(
    .INIT ( 64'h7007522525520770 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr641  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [33]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [52]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [7]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [7])
  );
  LUT5 #(
    .INIT ( 32'h00101000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rdack_rdack_OR_520_o1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rdack_1245 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1673 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rdack_rdack_OR_520_o )
  );
  LUT6 #(
    .INIT ( 64'hAAAAAAAA88808088 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/full_int_rstpot  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/fullg ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3_2877 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd2_2878 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/full_int_3072 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/full_int_rstpot_5769 )
  );
  LUT6 #(
    .INIT ( 64'h7007522525520770 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr191  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [14]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [33]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/test_patt_sel_GND_24_o_equal_15_o_mmx_out ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [26]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [26])
  );
  LUT6 #(
    .INIT ( 64'h7007522525520770 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr231  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [38]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [57]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/test_patt_sel_GND_24_o_equal_15_o_mmx_out ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [2])
  );
  LUT6 #(
    .INIT ( 64'h7007522525520770 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr451  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [36]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [55]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/test_patt_sel_GND_24_o_equal_15_o_mmx_out ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [4]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [4])
  );
  LUT6 #(
    .INIT ( 64'h7007522525520770 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr631  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [34]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [53]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/test_patt_sel_GND_24_o_equal_15_o_mmx_out ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [6]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [6])
  );
  LUT6 #(
    .INIT ( 64'h7007522525520770 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr651  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [32]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [51]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/test_patt_sel_GND_24_o_equal_15_o_mmx_out ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [8]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [8])
  );
  LUT6 #(
    .INIT ( 64'hEBEBC369BEBE963C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr551  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [18]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [59]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [59])
  );
  LUT6 #(
    .INIT ( 64'hEBEBC369BEBE963C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr531  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [16]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [57]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [57])
  );
  LUT6 #(
    .INIT ( 64'hEBEBC369BEBE963C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr521  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [15]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [56]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [56])
  );
  LUT6 #(
    .INIT ( 64'hEBEBC369BEBE963C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr511  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [14]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [4]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [55]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [55])
  );
  LUT6 #(
    .INIT ( 64'h7007522525520770 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr501  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [5]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [13]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [54]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [54])
  );
  LUT6 #(
    .INIT ( 64'h7007522525520770 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr491  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [6]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [12]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [53]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [53])
  );
  LUT6 #(
    .INIT ( 64'h7007522525520770 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr481  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [7]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [11]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [52]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [52])
  );
  LUT6 #(
    .INIT ( 64'h7007522525520770 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr471  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [8]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [10]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [51]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [51])
  );
  LUT6 #(
    .INIT ( 64'h7007522525520770 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr461  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [9]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [9]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [50]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [50])
  );
  LUT6 #(
    .INIT ( 64'h7007522525520770 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr441  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [10]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [8]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [49]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [49])
  );
  LUT6 #(
    .INIT ( 64'h7007522525520770 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr431  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [11]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [7]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [48]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [48])
  );
  LUT6 #(
    .INIT ( 64'h7007522525520770 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr421  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [12]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [6]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [47]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [47])
  );
  LUT6 #(
    .INIT ( 64'h7007522525520770 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr411  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [13]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [5]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [46]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [46])
  );
  LUT6 #(
    .INIT ( 64'h7007522525520770 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr401  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [14]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [4]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [45]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [45])
  );
  LUT6 #(
    .INIT ( 64'h7007522525520770 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr391  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [15]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [44]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [44])
  );
  LUT6 #(
    .INIT ( 64'hEBEBC369BEBE963C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr381  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [16]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [43]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [43])
  );
  LUT6 #(
    .INIT ( 64'hEBEBC369BEBE963C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr371  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [17]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [42]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [42])
  );
  LUT6 #(
    .INIT ( 64'hEBEBC369BEBE963C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr361  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [18]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [41]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [41])
  );
  LUT6 #(
    .INIT ( 64'hEBEBC369BEBE963C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr621  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [24]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [5]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [65]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [65])
  );
  LUT6 #(
    .INIT ( 64'hEBEBC369BEBE963C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr611  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [23]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [4]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [64]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [64])
  );
  LUT6 #(
    .INIT ( 64'hEBEBC369BEBE963C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr601  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [22]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [63]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [63])
  );
  LUT6 #(
    .INIT ( 64'hEBEBC369BEBE963C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr591  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [21]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [62]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [62])
  );
  LUT6 #(
    .INIT ( 64'hEBEBC369BEBE963C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr581  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [20]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [61]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [61])
  );
  LUT6 #(
    .INIT ( 64'hEBEBC369BEBE963C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr571  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_comb [19]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [60]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [60])
  );
  LUT6 #(
    .INIT ( 64'hEBEBC369BEBE963C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr351  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [19]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [40]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [40])
  );
  LUT6 #(
    .INIT ( 64'hEBEBC369BEBE963C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr331  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [20]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [39]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [39])
  );
  LUT6 #(
    .INIT ( 64'hEBEBC369BEBE963C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr321  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [21]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [38]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [38])
  );
  LUT6 #(
    .INIT ( 64'hEBEBC369BEBE963C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr311  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [22]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [3]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [37]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [37])
  );
  LUT6 #(
    .INIT ( 64'hEBEBC369BEBE963C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr301  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [23]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [4]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [36]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [36])
  );
  LUT6 #(
    .INIT ( 64'hEBEBC369BEBE963C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr291  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [24]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [5]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [35]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [35])
  );
  LUT6 #(
    .INIT ( 64'hEBEBC369BEBE963C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr281  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [25]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [6]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [34]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [34])
  );
  LUT6 #(
    .INIT ( 64'hEBEBC369BEBE963C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr271  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [26]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [7]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [33]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [33])
  );
  LUT6 #(
    .INIT ( 64'h7007522525520770 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr261  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [8]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [27]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [32]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [32])
  );
  LUT6 #(
    .INIT ( 64'h7007522525520770 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr251  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [9]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [28]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [31]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [31])
  );
  LUT6 #(
    .INIT ( 64'h7007522525520770 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr241  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [29]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [10]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [30]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [30])
  );
  LUT6 #(
    .INIT ( 64'h7007522525520770 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr221  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [30]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [11]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [29]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [29])
  );
  LUT6 #(
    .INIT ( 64'h7007522525520770 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr211  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [31]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [12]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [28]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [28])
  );
  LUT6 #(
    .INIT ( 64'h7007522525520770 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr201  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [32]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [13]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [27]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [27])
  );
  LUT6 #(
    .INIT ( 64'h5155555555555555 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_6_glue_set_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT204_5486 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [6]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [4]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [5]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n09151_3483 ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[47]_PWR_23_o_equal_134_o_mmx_out ),
    .O(N622)
  );
  LUT5 #(
    .INIT ( 32'h00000800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_0/Mmux_q[0]_d[0]_MUX_691_o11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15_we ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I4
(\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15/q_0 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_0/q[0]_d[0]_MUX_691_o )
  );
  LUT5 #(
    .INIT ( 32'h00000800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_11/Mmux_q[0]_d[0]_MUX_691_o11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15_we ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [11]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I4
(\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15/q_0 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_11/q[0]_d[0]_MUX_691_o )
  );
  LUT6 #(
    .INIT ( 64'h1000100010101000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT51  (
    .I0
(\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15/q_0 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [17]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [16]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_PWR_46_o_equal_60_o ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_35_o<15>1_1724 )
,
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT5 )
  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/Mmux_q[9]_d[9]_mux_3_OUT11  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_PWR_46_o_equal_57_o<15>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [0]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q[9]_d[9]_mux_3_OUT<0> )

  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/Mmux_q[9]_d[9]_mux_3_OUT21  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_PWR_46_o_equal_57_o<15>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q[9]_d[9]_mux_3_OUT<1> )

  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/Mmux_q[9]_d[9]_mux_3_OUT31  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_PWR_46_o_equal_57_o<15>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q[9]_d[9]_mux_3_OUT<2> )

  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/Mmux_q[9]_d[9]_mux_3_OUT41  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_PWR_46_o_equal_57_o<15>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q[9]_d[9]_mux_3_OUT<3> )

  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/Mmux_q[9]_d[9]_mux_3_OUT51  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_PWR_46_o_equal_57_o<15>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [4]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q[9]_d[9]_mux_3_OUT<4> )

  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/Mmux_q[9]_d[9]_mux_3_OUT61  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_PWR_46_o_equal_57_o<15>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [5]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q[9]_d[9]_mux_3_OUT<5> )

  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/Mmux_q[9]_d[9]_mux_3_OUT71  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_PWR_46_o_equal_57_o<15>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [6]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q[9]_d[9]_mux_3_OUT<6> )

  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/Mmux_q[9]_d[9]_mux_3_OUT81  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_PWR_46_o_equal_57_o<15>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [7]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q[9]_d[9]_mux_3_OUT<7> )

  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/Mmux_q[9]_d[9]_mux_3_OUT91  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_PWR_46_o_equal_57_o<15>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [8]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q[9]_d[9]_mux_3_OUT<8> )

  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/Mmux_q[9]_d[9]_mux_3_OUT101  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_PWR_46_o_equal_57_o<15>1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [9]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_37_9_0/q[9]_d[9]_mux_3_OUT<9> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/Mmux_q[9]_d[9]_mux_3_OUT11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q[9]_d[9]_mux_3_OUT<0> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/Mmux_q[9]_d[9]_mux_3_OUT21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q[9]_d[9]_mux_3_OUT<1> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/Mmux_q[9]_d[9]_mux_3_OUT31  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q[9]_d[9]_mux_3_OUT<2> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/Mmux_q[9]_d[9]_mux_3_OUT41  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q[9]_d[9]_mux_3_OUT<3> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/Mmux_q[9]_d[9]_mux_3_OUT51  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [4]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q[9]_d[9]_mux_3_OUT<4> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/Mmux_q[9]_d[9]_mux_3_OUT61  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q[9]_d[9]_mux_3_OUT<5> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/Mmux_q[9]_d[9]_mux_3_OUT71  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [6]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q[9]_d[9]_mux_3_OUT<6> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/Mmux_q[9]_d[9]_mux_3_OUT81  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [7]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q[9]_d[9]_mux_3_OUT<7> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/Mmux_q[9]_d[9]_mux_3_OUT91  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [8]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q[9]_d[9]_mux_3_OUT<8> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/Mmux_q[9]_d[9]_mux_3_OUT101  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [9]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_41_9_0/q[9]_d[9]_mux_3_OUT<9> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/Mmux_q[15]_d[15]_mux_3_OUT17  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<0> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/Mmux_q[15]_d[15]_mux_3_OUT21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [10]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<10> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/Mmux_q[15]_d[15]_mux_3_OUT31  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [11]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<11> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/Mmux_q[15]_d[15]_mux_3_OUT41  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [12]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<12> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/Mmux_q[15]_d[15]_mux_3_OUT51  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [13]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<13> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/Mmux_q[15]_d[15]_mux_3_OUT61  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [14]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<14> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/Mmux_q[15]_d[15]_mux_3_OUT71  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [15]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<15> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/Mmux_q[15]_d[15]_mux_3_OUT81  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<1> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/Mmux_q[15]_d[15]_mux_3_OUT91  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<2> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/Mmux_q[15]_d[15]_mux_3_OUT101  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<3> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/Mmux_q[15]_d[15]_mux_3_OUT111  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [4]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<4> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/Mmux_q[15]_d[15]_mux_3_OUT121  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<5> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/Mmux_q[15]_d[15]_mux_3_OUT131  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [6]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<6> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/Mmux_q[15]_d[15]_mux_3_OUT141  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [7]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<7> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/Mmux_q[15]_d[15]_mux_3_OUT151  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [8]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<8> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/Mmux_q[15]_d[15]_mux_3_OUT161  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_we1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [9]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_all/q[15]_d[15]_mux_3_OUT<9> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/Mmux_q[15]_d[15]_mux_3_OUT17  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<0> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/Mmux_q[15]_d[15]_mux_3_OUT21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [10]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<10> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/Mmux_q[15]_d[15]_mux_3_OUT31  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [11]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<11> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/Mmux_q[15]_d[15]_mux_3_OUT41  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [12]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<12> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/Mmux_q[15]_d[15]_mux_3_OUT51  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [13]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<13> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/Mmux_q[15]_d[15]_mux_3_OUT61  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [14]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<14> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/Mmux_q[15]_d[15]_mux_3_OUT71  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [15]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<15> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/Mmux_q[15]_d[15]_mux_3_OUT81  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<1> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/Mmux_q[15]_d[15]_mux_3_OUT91  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<2> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/Mmux_q[15]_d[15]_mux_3_OUT101  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<3> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/Mmux_q[15]_d[15]_mux_3_OUT111  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [4]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<4> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/Mmux_q[15]_d[15]_mux_3_OUT121  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<5> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/Mmux_q[15]_d[15]_mux_3_OUT131  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [6]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<6> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/Mmux_q[15]_d[15]_mux_3_OUT141  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [7]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<7> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/Mmux_q[15]_d[15]_mux_3_OUT151  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [8]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<8> )

  );
  LUT6 #(
    .INIT ( 64'h0000000000800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/Mmux_q[15]_d[15]_mux_3_OUT161  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [9]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q[15]_d[15]_mux_3_OUT<9> )

  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/Mmux_q[15]_d[15]_mux_3_OUT17  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<0> )

  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/Mmux_q[15]_d[15]_mux_3_OUT21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [10]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<10> )

  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/Mmux_q[15]_d[15]_mux_3_OUT31  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [11]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<11> )

  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/Mmux_q[15]_d[15]_mux_3_OUT41  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [12]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<12> )

  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/Mmux_q[15]_d[15]_mux_3_OUT51  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [13]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<13> )

  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/Mmux_q[15]_d[15]_mux_3_OUT61  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [14]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<14> )

  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/Mmux_q[15]_d[15]_mux_3_OUT71  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [15]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<15> )

  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/Mmux_q[15]_d[15]_mux_3_OUT81  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<1> )

  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/Mmux_q[15]_d[15]_mux_3_OUT91  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<2> )

  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/Mmux_q[15]_d[15]_mux_3_OUT101  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<3> )

  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/Mmux_q[15]_d[15]_mux_3_OUT111  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [4]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<4> )

  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/Mmux_q[15]_d[15]_mux_3_OUT121  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [5]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<5> )

  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/Mmux_q[15]_d[15]_mux_3_OUT131  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [6]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<6> )

  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/Mmux_q[15]_d[15]_mux_3_OUT141  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [7]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<7> )

  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/Mmux_q[15]_d[15]_mux_3_OUT151  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [8]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<8> )

  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/Mmux_q[15]_d[15]_mux_3_OUT161  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [9]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_we1_1717 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q[15]_d[15]_mux_3_OUT<9> )

  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/Mmux_q[15]_d[15]_mux_3_OUT17  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [0]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<0> )

  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/Mmux_q[15]_d[15]_mux_3_OUT21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [10]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<10> )

  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/Mmux_q[15]_d[15]_mux_3_OUT31  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [11]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<11> )

  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/Mmux_q[15]_d[15]_mux_3_OUT41  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [12]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<12> )

  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/Mmux_q[15]_d[15]_mux_3_OUT51  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [13]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<13> )

  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/Mmux_q[15]_d[15]_mux_3_OUT61  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [14]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<14> )

  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/Mmux_q[15]_d[15]_mux_3_OUT71  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [15]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<15> )

  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/Mmux_q[15]_d[15]_mux_3_OUT81  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<1> )

  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/Mmux_q[15]_d[15]_mux_3_OUT91  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<2> )

  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/Mmux_q[15]_d[15]_mux_3_OUT101  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<3> )

  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/Mmux_q[15]_d[15]_mux_3_OUT111  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [4]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<4> )

  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/Mmux_q[15]_d[15]_mux_3_OUT121  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [5]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<5> )

  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/Mmux_q[15]_d[15]_mux_3_OUT131  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [6]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<6> )

  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/Mmux_q[15]_d[15]_mux_3_OUT141  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [7]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<7> )

  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/Mmux_q[15]_d[15]_mux_3_OUT151  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [8]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<8> )

  );
  LUT6 #(
    .INIT ( 64'h2000000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/Mmux_q[15]_d[15]_mux_3_OUT161  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_we1_1718 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65522_addrdecode1 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [9]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_38_all/q[15]_d[15]_mux_3_OUT<9> )

  );
  LUT5 #(
    .INIT ( 32'hEEFEEEEE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/Mmux_q[15]_GND_56_o_mux_4_OUT17  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [0]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<0> )

  );
  LUT5 #(
    .INIT ( 32'hEEFEEEEE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/Mmux_q[15]_GND_56_o_mux_4_OUT21  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [10]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<10> )

  );
  LUT5 #(
    .INIT ( 32'hEEFEEEEE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/Mmux_q[15]_GND_56_o_mux_4_OUT31  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [11]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<11> )

  );
  LUT5 #(
    .INIT ( 32'h00000008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/Mmux_q[15]_GND_56_o_mux_4_OUT41  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [12]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I4(reset),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<12> )

  );
  LUT5 #(
    .INIT ( 32'h00000008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/Mmux_q[15]_GND_56_o_mux_4_OUT51  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [13]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I4(reset),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<13> )

  );
  LUT5 #(
    .INIT ( 32'hEEFEEEEE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/Mmux_q[15]_GND_56_o_mux_4_OUT61  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [14]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<14> )

  );
  LUT5 #(
    .INIT ( 32'h00000008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/Mmux_q[15]_GND_56_o_mux_4_OUT71  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [15]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I4(reset),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<15> )

  );
  LUT5 #(
    .INIT ( 32'hEEFEEEEE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/Mmux_q[15]_GND_56_o_mux_4_OUT81  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<1> )

  );
  LUT5 #(
    .INIT ( 32'h00000008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/Mmux_q[15]_GND_56_o_mux_4_OUT91  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I4(reset),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<2> )

  );
  LUT5 #(
    .INIT ( 32'hEEFEEEEE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/Mmux_q[15]_GND_56_o_mux_4_OUT101  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<3> )

  );
  LUT5 #(
    .INIT ( 32'h00000008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/Mmux_q[15]_GND_56_o_mux_4_OUT111  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [4]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I4(reset),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<4> )

  );
  LUT5 #(
    .INIT ( 32'h00000008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/Mmux_q[15]_GND_56_o_mux_4_OUT121  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [5]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I4(reset),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<5> )

  );
  LUT5 #(
    .INIT ( 32'hEEFEEEEE ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/Mmux_q[15]_GND_56_o_mux_4_OUT131  (
    .I0(reset),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [6]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<6> )

  );
  LUT5 #(
    .INIT ( 32'h00000008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/Mmux_q[15]_GND_56_o_mux_4_OUT141  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [7]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I4(reset),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<7> )

  );
  LUT5 #(
    .INIT ( 32'h00000008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/Mmux_q[15]_GND_56_o_mux_4_OUT151  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [8]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I4(reset),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<8> )

  );
  LUT5 #(
    .INIT ( 32'h00000008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/Mmux_q[15]_GND_56_o_mux_4_OUT161  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [9]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I4(reset),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q[15]_GND_56_o_mux_4_OUT<9> )

  );
  LUT6 #(
    .INIT ( 64'hEEEEEFEE44444044 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mmux_timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4227 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<0> ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4510 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [0]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<0> )

  );
  LUT6 #(
    .INIT ( 64'hFFFF04FFFFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT54  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [4]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n09151_3483 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [5]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1141 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_PWR_23_o_equal_166_o ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[39]_tx_xgmii_data_reg1[39]_OR_153_o_3588 )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT53_5411 )
  );
  LUT6 #(
    .INIT ( 64'hAAAAAAAAAAAABAAA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT206_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/reset_local_429 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [6]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n09151_3483 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[63]_PWR_23_o_equal_148_o ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [5]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [4]),
    .O(N392)
  );
  LUT6 #(
    .INIT ( 64'hAAAAAAAAAAAABAAA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_addr<3>_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [5]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1361 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ),
    .O(N12)
  );
  LUT6 #(
    .INIT ( 64'hAAAAAAAAAAAABAAA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_addr<4>_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [4]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [5]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1361 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ),
    .O(N14)
  );
  LUT6 #(
    .INIT ( 64'hAAAAAAAAAAAABAAA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_addr<6>_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [6]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [5]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1361 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ),
    .O(N16)
  );
  LUT6 #(
    .INIT ( 64'hAAAAAAAAAAAABAAA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_addr<8>_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [8]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [5]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1361 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ),
    .O(N18)
  );
  LUT6 #(
    .INIT ( 64'hAAAAAAAAAAAABAAA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_addr<2>_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [5]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1361 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ),
    .O(N20)
  );
  LUT6 #(
    .INIT ( 64'h00000020FFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_addr<1>_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [5]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1361 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [1]),
    .O(N22)
  );
  LUT6 #(
    .INIT ( 64'h00000020FFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_addr<5>_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [5]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1361 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [5]),
    .O(N24)
  );
  LUT6 #(
    .INIT ( 64'h00000020FFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_addr<7>_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [5]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1361 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [7]),
    .O(N26)
  );
  LUT6 #(
    .INIT ( 64'h00000020FFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_addr<9>_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [5]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1361 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [9]),
    .O(N28)
  );
  LUT6 #(
    .INIT ( 64'h00000020FFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_addr<10>_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [5]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1361 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [10]),
    .O(N30)
  );
  LUT6 #(
    .INIT ( 64'h00000020FFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_addr<11>_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [5]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1361 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [11]),
    .O(N32)
  );
  LUT6 #(
    .INIT ( 64'h00000020FFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_addr<12>_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [5]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1361 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [12]),
    .O(N34)
  );
  LUT6 #(
    .INIT ( 64'h00000020FFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_addr<13>_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [5]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1361 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [13]),
    .O(N36)
  );
  LUT6 #(
    .INIT ( 64'h00000020FFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_addr<14>_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [5]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1361 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [14]),
    .O(N38)
  );
  LUT6 #(
    .INIT ( 64'h00000020FFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_addr<15>_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [5]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1361 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [15]),
    .O(N40)
  );
  LUT6 #(
    .INIT ( 64'h00000020FFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_addr<0>_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [5]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1361 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [0]),
    .O(N42)
  );
  LUT6 #(
    .INIT ( 64'h51555555FFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT9_SW0  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o<7>1 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [2]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o<7>1 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c1 [0]),
    .O(N198)
  );
  LUT6 #(
    .INIT ( 64'h51555555FFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT15_SW0  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o<7>1 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [2]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o<7>1 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c1 [5]),
    .O(N200)
  );
  LUT6 #(
    .INIT ( 64'h51555555FFFFFFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_mux_457_OUT16_SW0  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o<7>1 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [2]),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o<7>1 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/t_type_reg [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/c1 [6]),
    .O(N202)
  );
  LUT6 #(
    .INIT ( 64'hEEEEEFEE44444044 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mmux_timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT81  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4227 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<1> ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4510 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<1> )

  );
  LUT6 #(
    .INIT ( 64'hEEEEEFEE44444044 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mmux_timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT71  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4227 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<15> ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4510 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [15]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<15> )

  );
  LUT6 #(
    .INIT ( 64'hEEEEEFEE44444044 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mmux_timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT61  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4227 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<14> ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4510 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [14]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<14> )

  );
  LUT6 #(
    .INIT ( 64'hEEEEEFEE44444044 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mmux_timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT51  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4227 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<13> ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4510 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [13]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<13> )

  );
  LUT6 #(
    .INIT ( 64'hEEEEEFEE44444044 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mmux_timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT41  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4227 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<12> ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4510 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [12]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<12> )

  );
  LUT6 #(
    .INIT ( 64'hEEEEEFEE44444044 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mmux_timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT31  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4227 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<11> ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4510 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [11]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<11> )

  );
  LUT6 #(
    .INIT ( 64'hEEEEEFEE44444044 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mmux_timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4227 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<10> ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4510 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [10]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<10> )

  );
  LUT6 #(
    .INIT ( 64'hEEEEEFEE44444044 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mmux_timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT161  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4227 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<9> ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4510 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [9]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<9> )

  );
  LUT6 #(
    .INIT ( 64'hEEEEEFEE44444044 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mmux_timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT151  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4227 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<8> ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4510 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [8]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<8> )

  );
  LUT6 #(
    .INIT ( 64'hEEEEEFEE44444044 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mmux_timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT141  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4227 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<7> ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4510 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [7]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<7> )

  );
  LUT6 #(
    .INIT ( 64'hEEEEEFEE44444044 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mmux_timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT131  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4227 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<6> ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4510 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [6]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<6> )

  );
  LUT6 #(
    .INIT ( 64'hEEEEEFEE44444044 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mmux_timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT121  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4227 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<5> ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4510 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [5]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<5> )

  );
  LUT6 #(
    .INIT ( 64'hEEEEEFEE44444044 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mmux_timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT111  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4227 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<4> ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4510 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [4]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<4> )

  );
  LUT6 #(
    .INIT ( 64'hEEEEEFEE44444044 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mmux_timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT101  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4227 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<3> ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4510 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<3> )

  );
  LUT6 #(
    .INIT ( 64'hEEEEEFEE44444044 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Mmux_timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT91  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2_4227 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_GND_27_o_sub_21_OUT<2> ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd2_4462 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd3_4509 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/state_FSM_FFd1_4510 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65535_all/q [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us[15]_timer_125us_cycles[15]_mux_31_OUT<2> )

  );
  LUT5 #(
    .INIT ( 32'h4E444444 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15/q_0_rstpot  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15_we ),
    .I1
(\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15/q_0 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [15]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_15/q_0_rstpot_5764 )
  );
  LUT6 #(
    .INIT ( 64'hEAAAAAAAAAAAAAAA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<60>11  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<57>11 )
,
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [7]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [6]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [5]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [4]),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o<7>1 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<60>1 )
  );
  LUT4 #(
    .INIT ( 16'h0800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/Mmux_q[15]_d[15]_mux_3_OUT17  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_we ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [0]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<0> )

  );
  LUT4 #(
    .INIT ( 16'h0800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/Mmux_q[15]_d[15]_mux_3_OUT21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_we ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [10]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<10> )

  );
  LUT4 #(
    .INIT ( 16'h0800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/Mmux_q[15]_d[15]_mux_3_OUT31  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_we ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [11]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<11> )

  );
  LUT4 #(
    .INIT ( 16'h0800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/Mmux_q[15]_d[15]_mux_3_OUT41  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_we ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [12]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<12> )

  );
  LUT4 #(
    .INIT ( 16'h0800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/Mmux_q[15]_d[15]_mux_3_OUT51  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_we ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [13]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<13> )

  );
  LUT4 #(
    .INIT ( 16'h0800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/Mmux_q[15]_d[15]_mux_3_OUT61  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_we ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [14]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<14> )

  );
  LUT4 #(
    .INIT ( 16'h0800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/Mmux_q[15]_d[15]_mux_3_OUT71  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_we ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [15]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<15> )

  );
  LUT4 #(
    .INIT ( 16'h0800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/Mmux_q[15]_d[15]_mux_3_OUT81  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_we ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<1> )

  );
  LUT4 #(
    .INIT ( 16'h0800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/Mmux_q[15]_d[15]_mux_3_OUT91  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_we ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<2> )

  );
  LUT4 #(
    .INIT ( 16'h0800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/Mmux_q[15]_d[15]_mux_3_OUT101  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_we ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<3> )

  );
  LUT4 #(
    .INIT ( 16'h0800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/Mmux_q[15]_d[15]_mux_3_OUT111  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_we ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [4]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<4> )

  );
  LUT4 #(
    .INIT ( 16'h0800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/Mmux_q[15]_d[15]_mux_3_OUT121  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_we ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [5]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<5> )

  );
  LUT4 #(
    .INIT ( 16'h0800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/Mmux_q[15]_d[15]_mux_3_OUT131  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_we ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [6]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<6> )

  );
  LUT4 #(
    .INIT ( 16'h0800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/Mmux_q[15]_d[15]_mux_3_OUT141  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_we ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [7]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<7> )

  );
  LUT4 #(
    .INIT ( 16'h0800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/Mmux_q[15]_d[15]_mux_3_OUT151  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_we ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [8]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<8> )

  );
  LUT4 #(
    .INIT ( 16'h0800 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/Mmux_q[15]_d[15]_mux_3_OUT161  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_we ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [9]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_65521_all/q[15]_d[15]_mux_3_OUT<9> )

  );
  LUT5 #(
    .INIT ( 32'h4E444444 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_rstpot  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15_we ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [15]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_rstpot_5765 )
  );
  LUT5 #(
    .INIT ( 32'h00800000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_366_o1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_cs ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [16]),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/pcs_addr[15]_GND_64_o_equal_29_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [5]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/ipif_rdack_prbs31_rx_enable_core_AND_366_o )

  );
  LUT6 #(
    .INIT ( 64'h0001000100010000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_0_glue_set_SW0  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[1]_AND_52_o )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[2]_AND_57_o )
,
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[3]_AND_61_o )
,
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[4]_AND_64_o )
,
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1172_5470 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT21 ),
    .O(N666)
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFEAAA2AAA ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_0_glue_set  (
    .I0(N666),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out231 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT11321 ),
    .I5(N392),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_0_glue_set_5693 )
  );
  LUT6 #(
    .INIT ( 64'h000100050003000F ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT324_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/dec_c4_6_4974 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [48]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_306_o ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_312_o ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<24>2 ),
    .I5
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<24>1 ),
    .O(N668)
  );
  LUT6 #(
    .INIT ( 64'h0F0F0D000F0F0D0D ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT324  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_GND_30_o_equal_310_o ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT321_5589 )
,
    .I5(N668),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<38> )
  );
  LUT4 #(
    .INIT ( 16'h0013 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT19_SW1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [36]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_PWR_32_o_equal_305_o ),
    .I2
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<39>2 ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_reg[7]_dec_c7[7]_select_316_OUT<39>3 ),
    .O(N670)
  );
  LUT6 #(
    .INIT ( 64'h00AA000000FB00F3 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT19  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [28]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5_4224 ),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/Mmux_rx_64_data_out[63]_GND_30_o_mux_322_OUT111_4674 )
,
    .I5(N670),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_64_data_out[63]_GND_30_o_mux_322_OUT<26> )
  );
  LUT6 #(
    .INIT ( 64'h0001000000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_36_o<15>1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [5]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_0_addrdecode1_1732 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_36_o )
  );
  LUT5 #(
    .INIT ( 32'hFFFF0008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<25>11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [7]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_443_o<7>1_3480 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [4]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<52>31 )
,
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_d7[7]_select_456_OUT<25>1 )
  );
  LUT5 #(
    .INIT ( 32'h80000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o<7>2  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [7]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [6]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [5]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg [4]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_GND_22_o_equal_452_o<7>1 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2_reg[7]_PWR_23_o_equal_444_o )
  );
  LUT6 #(
    .INIT ( 64'h8000000080008000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_re1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_addrdecode1 ),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[15]_GND_44_o_equal_44_o<15>1_1726 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/regs_cs ),
    .I3
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/addr[20]_GND_44_o_equal_101_o<20>1 )
,
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_43_re )
  );
  LUT6 #(
    .INIT ( 64'h1111111011111111 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n085421  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[3]_AND_61_o )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[4]_AND_64_o )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [2]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/out231 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT171_5327 )
  );
  LUT3 #(
    .INIT ( 8'hF2 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_glue_set  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_1672 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/rdack_1245 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1361 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/read_reg_glue_set_5674 )
  );
  LUT4 #(
    .INIT ( 16'h08FF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/block_field_2_glue_set_SW0  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [6]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/_n09151_3483 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1 [4]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT83_5325 ),
    .O(N624)
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFDFDFDA8 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/_n0084<4>1  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/state[3]_bit_count[4]_AND_351_o ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [3]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [3]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/devad_reg [4]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/devad [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/_n0084 )
  );
  LUT6 #(
    .INIT ( 64'h7007522525520770 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr21  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [30]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [49]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [10]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [10])
  );
  LUT6 #(
    .INIT ( 64'hEBEBC369BEBE963C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr31  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [48]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [29]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [11]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [11])
  );
  LUT6 #(
    .INIT ( 64'hEBEBC369BEBE963C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr41  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [47]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [28]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [12]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [12])
  );
  LUT6 #(
    .INIT ( 64'hEBEBC369BEBE963C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr51  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [46]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [27]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [13]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [13])
  );
  LUT6 #(
    .INIT ( 64'hEBEBC369BEBE963C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr91  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [42]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [23]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [17]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [17])
  );
  LUT6 #(
    .INIT ( 64'hEBEBC369BEBE963C ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr101  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [41]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [22]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [18]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [18])
  );
  LUT6 #(
    .INIT ( 64'h7007522525520770 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mmux_tx_66_scr661  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [3]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [31]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/scr_reg [50]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/tx_test_patt_seed_sel [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_pcs_fsm_i/tx_66_enc_out [9]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/tx_66_scr_int [9])
  );
  LUT5 #(
    .INIT ( 32'h4E444444 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_9_0/q_0_rstpot  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_9_we ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/synch_4/d ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_1_9_0/q_0_rstpot_5766 )
  );
  LUT6 #(
    .INIT ( 64'h02000200AAAA0200 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_1_2/q_0_rstpot1  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_32_12/q_0_1956 ),
    .I1(reset),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_1_2/q_0_1957 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_1_re ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_1_2/re_prev_1757 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_1_2/q_0_rstpot1_5800 )
  );
  LUT6 #(
    .INIT ( 64'h2222262222222222 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_1_glue_set  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_1_3392 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ),
    .I2(\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/q ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_test_mode_int_reg_501 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_2_3394 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/err_block_count_inc_out_554 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_1_glue_set_5677 )
  );
  LUT6 #(
    .INIT ( 64'h2222622222222222 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_3_glue_set  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_3_3393 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_test_mode_int_reg_501 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/err_block_count_inc_out_554 ),
    .I4(\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/q ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_2_3394 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_3_glue_set_5678 )
  );
  LUT6 #(
    .INIT ( 64'h2222622222222222 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_2_glue_set  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_2_3394 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_test_mode_int_reg_501 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/err_block_count_inc_out_554 ),
    .I4(\NlwRenamedSig_OI_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/clk156_rxusrclk2_resyncs_i/resynch[4].synch_inst/q ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_1_3392 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/test_err_block_counter_i/counter_2_glue_set_5679 )
  );
  LUT5 #(
    .INIT ( 32'h22262222 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_1_glue_set  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_1_3412 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_test_mode_int_reg_501 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_2_3414 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/err_block_count_inc_out_554 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_1_glue_set_5680 )
  );
  LUT5 #(
    .INIT ( 32'h46444444 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_3_glue_set  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_3_3413 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_test_mode_int_reg_501 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/err_block_count_inc_out_554 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_2_3414 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_3_glue_set_5681 )
  );
  LUT5 #(
    .INIT ( 32'h46444444 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_2_glue_set  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_2_3414 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_test_mode_int_reg_501 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/err_block_count_inc_out_554 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_1_3412 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/norm_err_block_counter_i/counter_2_glue_set_5682 )
  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_11/Mmux_q[0]_d[0]_MUX_691_o11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [11]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15_we ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I4(reset),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_11/q[0]_d[0]_MUX_691_o )
  );
  LUT6 #(
    .INIT ( 64'h0000002000000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_14/Mmux_q[0]_d[0]_MUX_691_o11  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/shift_reg [14]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15_we ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_15/q_0_1958 ),
    .I4(reset),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_0_14/q[0]_d[0]_MUX_691_o )
  );
  MUXF7   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_next_state23  (
    .I0(N672),
    .I1(N673),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/next_state [1])
  );
  LUT5 #(
    .INIT ( 32'h00101111 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_next_state23_F  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd1_5067 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2_5068 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5069 ),
    .O(N672)
  );
  LUT6 #(
    .INIT ( 64'h0004000400040404 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_next_state23_G  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [2]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5069 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd1_5067 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next_reg [0]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next_reg [2]),
    .O(N673)
  );
  MUXF7   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_next_state33  (
    .I0(N674),
    .I1(N675),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/next_state [2])
  );
  LUT5 #(
    .INIT ( 32'hFFFF882A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_next_state33_F  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5069 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd2_5068 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd1_5067 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [2]),
    .O(N674)
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFFFFA8FFFF ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/Mmux_next_state33_G  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next_reg [2]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_next_reg [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/r_type_reg [2]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd3_5069 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/state_FSM_FFd1_5067 ),
    .O(N675)
  );
  MUXF7   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code73  (
    .I0(N676),
    .I1(N677),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [51]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code72 )
  );
  LUT6 #(
    .INIT ( 64'h8000000000000008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code73_F  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [48]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [49]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [54]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [53]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [52]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [55]),
    .O(N676)
  );
  LUT6 #(
    .INIT ( 64'h4004040404000004 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code73_G  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [48]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [52]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [49]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [55]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [54]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [53]),
    .O(N677)
  );
  MUXF7   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code13  (
    .I0(N678),
    .I1(N679),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [3]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code12 )
  );
  LUT6 #(
    .INIT ( 64'h8000000000000008 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code13_F  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [7]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [5]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [4]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [6]),
    .O(N678)
  );
  LUT6 #(
    .INIT ( 64'h4004040404000004 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_tx_xgmii_valid_code13_G  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [4]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [1]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [7]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [6]),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [5]),
    .O(N679)
  );
  MUXF7   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3-In2  (
    .I0(N680),
    .I1(N681),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3_1673 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3-In )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFF66764454 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3-In2_F  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd2_1674 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/indirect_read_1676 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_we_rising_1339 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/mgmt_rdack ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1361 ),
    .O(N680)
  );
  LUT5 #(
    .INIT ( 32'hFFFF082A ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd3-In2_G  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/ipif_access_inst/state_FSM_FFd1_1675 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_cs ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_2/q [17]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/wrack_1244 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/rd_1361 ),
    .O(N681)
  );
  MUXF7 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT97  (
    .I0(N682),
    .I1(N683),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT96 )

  );
  LUT4 #(
    .INIT ( 16'h7351 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT97_F  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_33_7_0/q [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_34_all/q [2]),
    .O(N682)
  );
  LUT5 #(
    .INIT ( 32'hFBEA5140 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT97_G  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [0]),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/addr_reg [1]),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_42_5_0/q [2]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/reg_3_40_all/q [2]),
    .I4
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_registers_i/common_reg_block/Mmux_GND_44_o_GND_44_o_mux_65_OUT94_5183 )
,
    .O(N683)
  );
  MUXF7   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd2-In3  (
    .I0(N684),
    .I1(N685),
    .S(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd1_2879 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd2-In )
  );
  LUT5 #(
    .INIT ( 32'h46444444 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd2-In3_F  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd2_2878 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd3_2877 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd2-In1_5312 )
,
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/status [3]),
    .O(N684)
  );
  LUT5 #(
    .INIT ( 32'h4E444444 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd2-In3_G  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156 ),
    .I1(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/state_FSM_FFd2_2878 ),
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_idle [0]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/idle_delete_i/input_is_idle [1]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/status [3]),
    .O(N685)
  );
  MUXF7   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1177  (
    .I0(N686),
    .I1(N687),
    .S
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[2]_AND_57_o )
,
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1176_5473 )
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFF11111110 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1177_F  (
    .I0
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[3]_AND_61_o )
,
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg1[7]_tx_xgmii_ctrl_reg1[4]_AND_64_o )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT117111 ),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1173 ),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1172_5470 ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1175 ),
    .O(N686)
  );
  LUT6 #(
    .INIT ( 64'hFFFFFFFF40000000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1177_G  (
    .I0(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [25]),
    .I1
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1[31]_tx_xgmii_data_reg1[31]_OR_80_o2 )
,
    .I2(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [24]),
    .I3(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_data_reg1 [27]),
    .I4(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_valid_code[7]_reduce_and_188_o ),
    .I5(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/Mmux_GND_22_o_GND_22_o_mux_219_OUT1175 ),
    .O(N687)
  );
  INV 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_lut<0>_INV_0  (
    .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/an_addr_int [0]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_an_addr_int[15]_GND_63_o_add_136_OUT_lut<0> )

  );
  INV 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_lut<0>_INV_0  (
    .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pma_addr_int [0]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pma_addr_int[15]_GND_63_o_add_130_OUT_lut<0> )

  );
  INV 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_lut<0>_INV_0  (
    .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/pcs_addr_int [0]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/management_mdio_i/mdio_interface_i/Madd_pcs_addr_int[15]_GND_63_o_add_133_OUT_lut<0> )

  );
  INV 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_lut<0>_INV_0  (
    .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_test_pattern_error_count [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_test_pattern_error_count_lut [0])
  );
  INV   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_lut<0>_INV_0  (
    .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_error_block_count [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_error_block_count_lut [0])
  );
  INV 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<15>_INV_0  (
    .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [15]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<15> )
  );
  INV 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<14>_INV_0  (
    .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [14]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<14> )
  );
  INV 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<13>_INV_0  (
    .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [13]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<13> )
  );
  INV 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<12>_INV_0  (
    .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [12]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<12> )
  );
  INV 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<11>_INV_0  (
    .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [11]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<11> )
  );
  INV 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<10>_INV_0  (
    .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [10]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<10> )
  );
  INV 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<9>_INV_0  (
    .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [9]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<9> )
  );
  INV 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<8>_INV_0  (
    .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [8]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<8> )
  );
  INV 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<7>_INV_0  (
    .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [7]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<7> )
  );
  INV 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<6>_INV_0  (
    .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [6]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<6> )
  );
  INV 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<5>_INV_0  (
    .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [5]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<5> )
  );
  INV 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<4>_INV_0  (
    .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [4]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<4> )
  );
  INV 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<3>_INV_0  (
    .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [3]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<3> )
  );
  INV 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<2>_INV_0  (
    .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [2]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<2> )
  );
  INV 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<1>_INV_0  (
    .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/timer_125us [1]),
    .O
(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/Msub_timer_125us[15]_GND_27_o_sub_21_OUT_lut<1> )
  );
  INV   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_INV_322_o1_INV_0  (
    .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_2081 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_en_INV_322_o )
  );
  INV   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Mcount_pcs_ber_count_xor<0>11_INV_0  (
    .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/pcs_ber_count [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/ieee_counters_i/Result [0])
  );
  INV   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Mcount_rd_addr_xor<0>11_INV_0  (
    .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/rd_addr[0] ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Result<0>1 )
  );
  INV   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Mcount_wr_addr_xor<0>11_INV_0  (
    .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/wr_addr[0] ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/Result [0])
  );
  INV   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en1_INV_0  (
    .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/full_int_838 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/txratefifo_i/asynch_fifo_i/ram_wr_en )
  );
  INV 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Mcount_rd_addr_xor<0>11_INV_0  (
    .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/rd_addr [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Result<0>1 )
  );
  INV 
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Mcount_wr_addr_xor<0>11_INV_0  (
    .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/wr_addr [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/Result [0])
  );
  INV   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/full_int_inv1_INV_0  (
    .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/full_int_3072 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/rx_elastic_buffer_i/asynch_fifo_i/full_int_inv )
  );
  INV   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_inv1_INV_0  (
    .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxdatavalid_504 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_inv )
  );
  INV   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o_norst1_INV_0  (
    .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxheadervalid_503 ),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o_norst )
  );
  INV   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<7>_inv1_INV_0  (
    .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [7]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<7>_inv )
  );
  INV   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<6>_inv1_INV_0  (
    .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [6]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<6>_inv )
  );
  INV   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<5>_inv1_INV_0  (
    .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [5]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<5>_inv )
  );
  INV   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<4>_inv1_INV_0  (
    .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [4]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<4>_inv )
  );
  INV   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<3>_inv1_INV_0  (
    .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [3]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<3>_inv )
  );
  INV   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<2>_inv1_INV_0  (
    .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [2]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<2>_inv )
  );
  INV   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<0>_inv1_INV_0  (
    .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<0>_inv )
  );
  INV   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<1>_inv1_INV_0  (
    .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2 [1]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/tx_encoder_i/tx_xgmii_ctrl_reg2<1>_inv )
  );
  INV   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Mcount_block_count_xor<0>11_INV_0  (
    .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/block_count [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/tx_pcs_i/pcs_scramble_i/Result<0>1 )
  );
  INV   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Mcount_block_count_xor<0>11_INV_0  (
    .I(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/block_count [0]),
    .O(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_test_i/Result [0])
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxusrclk2_en156_1  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o_norst ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_inv ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_1 )
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxusrclk2_en156_2  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o_norst ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_inv ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_2 )
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxusrclk2_en156_3  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o_norst ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_inv ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_3 )
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxusrclk2_en156_4  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o_norst ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_inv ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_4 )
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxusrclk2_en156_5  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o_norst ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_inv ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_5 )
  );
  FDR   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxusrclk2_en156_6  (
    .C(rxusrclk2),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_rxheadervalid_AND_5_o_norst ),
    .R(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxratecounter_i/rxdatavalid_inv ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rxusrclk2_en156_6 )
  );
  SRLC16E #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mshreg_rd_addr2_1  (
    .A0(NlwRenamedSig_OI_drp_dwe),
    .A1(NlwRenamedSig_OI_drp_dwe),
    .A2(NlwRenamedSig_OI_drp_dwe),
    .A3(NlwRenamedSig_OI_drp_dwe),
    .CE(N0),
    .CLK(dclk),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd1_2080 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mshreg_rd_addr2_1_5968 ),
    .Q15(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mshreg_rd_addr2_1_Q15_UNCONNECTED )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2_1  (
    .C(dclk),
    .CE(N0),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mshreg_rd_addr2_1_5968 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [1])
  );
  SRLC16E #(
    .INIT ( 16'h0000 ))
  \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mshreg_rd_addr2_0  (
    .A0(NlwRenamedSig_OI_drp_dwe),
    .A1(NlwRenamedSig_OI_drp_dwe),
    .A2(NlwRenamedSig_OI_drp_dwe),
    .A3(NlwRenamedSig_OI_drp_dwe),
    .CE(N0),
    .CLK(dclk),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/wr_addr_FSM_FFd2_2079 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mshreg_rd_addr2_0_5969 ),
    .Q15(\NLW_U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mshreg_rd_addr2_0_Q15_UNCONNECTED )
  );
  FDE   \U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2_0  (
    .C(dclk),
    .CE(N0),
    .D(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/Mshreg_rd_addr2_0_5969 ),
    .Q(\U0/G_IS_GTX.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/management_inst/drp_ipif_i/synch_1/rd_addr2 [0])
  );

// synthesis translate_on

endmodule

// synthesis translate_off

`ifndef GLBL
`define GLBL

`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;

//--------   STARTUP Globals --------------
    wire GSR;
    wire GTS;
    wire GWE;
    wire PRLD;
    tri1 p_up_tmp;
    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;

    wire PROGB_GLBL;
    wire CCLKO_GLBL;

    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;
    reg JTAG_RUNTEST_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (weak1, weak0) GSR = GSR_int;
    assign (weak1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

endmodule

`endif

// synthesis translate_on
